Apple Inc.

André Seznec

Ronald P Hall

Ramesh B Gunna

Ian D Kountanis

Conrado Blasco

Shyam Sundar

A processor includes a mechanism for disabling a memory array of a branch prediction unit. The processor may include a next fetch prediction unit that may include a number of entries. Each entry may correspond to a next instruction fetch group and may store an indication of whether or not the corresponding the next fetch group includes a conditional branch instruction. In response to an indication that the next fetch group does not include a conditional branch instruction, the fetch prediction unit may be configured to disable, in a next instruction execution cycle, the memory array of the branch prediction unit.

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Acigné, France

André Seznec