International Business Machines Corporation

Andre R Steimle

Didier R Louis

Pascal R Tannhof

Guy Paillet

Bernard Desrosiers

Gerard Boudon

David Pereira

Catherine Godefroy

Didier Malcavet

Didier Pinchon

Jean-Yves Boulet

Louis Didier

Bernard Jung

A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Self-synchronizing bit error analyzer and circuit

The image sensing device interface unit attached to an image sensing device has dedicated means to detect a complete missing line and to perform clock gating of circuits for power management self-optimization. For each image frame, the time interval between start of lineand start of lineis computed and stored in a first register. The time interval between any other pair of two consecutive lines is also computed and stored in a second register. The stored values are compared, and if the value in the second register is greater than in the first register, a complete missing line has been detected and the gated clock used in said circuits is switched off for power saving. The interface unit can adapt to any type of sensor and does not require the help of any processor to perform the power saving function.

Image sensing device interface unit

A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator

Self-synchronising bit error analyser and circuit

A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the components of a first and second input vectors into the ANN; engaging all the neurons of a same prototype; having all the neurons compute their own distance between the respective prototypes and the second input vector (which should be the same if the neurons were good); determining the minimum distance Dmin and comparing Dmin with a distance D measured between the first and the second input vectors. If Dmin<D, it is indicative that at least one failing neuron exists (i.e., either the distance, the category or the AIF value differs from a predetermined expected value), in which case the failing neuron is isolated. If Dmin&gE;D, the good neurons of the ANN are deselected, preventing the good neurons from further learning/recognition processing; and repeating the previous steps until the ANN is empty. The present method provides a fast and inexpensive integrity diagnostic of the neurons forming an ANN at the cost of only a few logic gates.

Method and circuit for performing the integrity diagnostic of an artificial neural network

The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other. The selection between the two modes (single/dual) is made by the user which stores a specific logic value in a dedicated register of the control logic circuitry in each improved neuron.

Neuron architecture having a dual structure and neural networks incorporating the same

A method of achieving automatic learning of an input vector presented to an artificial neural network (ANN) formed by a plurality of neurons, using the K nearest neighbor (KNN) mode. Upon providing an input vector to be learned to the ANN, a Write component operation is performed to store the input vector components in the first available free neuron of the ANN. Then, a Write category operation is performed by assigning a category defined by the user to the input vector. Next, a test is performed to determine whether this category matches the categories of the nearest prototypes, i.e. which are located at the minimum distance. If it matches, this first free neuron is not engaged. Otherwise, it is engaged by assigning the matching category to it. As a result, the input vector becomes the new prototype with the matching category associated thereto. Further described is a circuit which automatically retains the first free neuron of the ANN for learning.

Implementing automatic learning according to the K nearest neighbor mode in artificial neural networks

A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the 'fire' type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. In a multi-chip network, an additional OR function is performed between all corresponding first global result and output signals (which are intermediate signals) to generate second global result (R**) and output (OUT**) signals, preferably by dotting onto an off-chip common communication bus (COM**-BUS) in the chip's driver block (19). This latter bus is shared by all the base neural network chips that are connected to it in order to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the intermediate output or the global output signal to be fed back to all neuron circuits of the neural network, depending on whether the chip is used in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal is the result of a collective processing of all the local output signals.

Neural semiconductor chip and neural networks incorporated therein

Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free 'or ready to learn' neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value. The DCI input of the first daisy chain circuit in the chain is connected to a second logic value, such that after initialization, it is the ready to learn neuron circuit. In the learning phase, the ready to learn neuron's 1-bit daisy register contents are set to the second logic value by the store enable signal, it is said 'engaged'. As neurons are engaged, each subsequent neuron circuit in the chain then becomes the next ready to learn neuron circuit.

Daisy chain circuit for serial connection of neuron circuits

In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) for addressing the weight memory and a register (253) to latch the data output on the output data bus. After the determined neuron circuit has been engaged, the contents of its weight memory cannot be modified. Pre-charging the input vector during the recognition phase makes the engagement process more efficient and significantly reduces learning time in learning the input vector.

Circuit for pre-charging a free neuron circuit

In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

Neuron circuit

An apparatus for executing argument reduction in the computation of F(x)=2**x-1 (with .vertline.x.vertline.&lt;1), determining the value of xi and computing (x-xi) according to the IEEE 754 standard floating-point format having a first circuit arrangement operative to perform pipeline operations on a N bit mantissa; the output of the first circuit arrangement being connected to a normalizer circuit of N+4 bits whose three left-most inputs are tied to 'zero' and whose three left-most out bits J(0:2) are output on a three-bits bus (J-BUS). Also incorporated is a leading zero detector/encoder circuit and a second circuit arrangement operative to perform pipeline operations on exponents connected to an encoder circuit whose output controls the aligner circuit and a selector circuit driven by the outputs of the detector/encoder circuit and encoder circuit whose output controls the normalizer circuit; a xi determining circuit that generates the xi mantissa on a xi-BUS connected to the first circuit arrangement such that: mantissa xi=0=K(1) K(2) 1 0 . . . , 0, and a read-only memory to store the F(xi) values whose output is connected to inputs of the first and second circuits for the respective mantissa and exponent parts of F(xi).

Apparatus for argument reduction in exponential computations of IEEE

A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.

System for optimizing argument reduction

A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0. In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the 'carry out' output. The 'Force Carry' input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.

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Evyr, France

Andre R Steimle