International Business Machines Corporation

Andre Masclet

Jean L Calvignac

Bernard Brezzo

Yves Granger

Richard Dambricourt

Jean-Pierre Sanche

A line scanning device which operates under the control of a microprocessor connected to a control memory in which a memory location area is assigned to each line is provided for a line adapter in a communication controller for receiving or sending message bits in series from or to terminals connected to the lines using any protocols. It comprises a first store which includes a first and a second memories, an area being assigned to each line in each of the memories which can be read and written in the same time and a second store which includes a single memory in which a storage location area is assigned to each line. These stores are addressed by a control and address unit which includes first and second address counters under the control of an elementary time counter, the first counter outputting the address information relating to the first store during time t provided for scanning a line, and the second counter outputting the address information relative to the second store during time nt, n being at least equal to 4, and control circuitry receiving said address information and the elementary time information for providing at the outputs of the control and address unit, memory address and read/write control information at times selected during the scanning period and sequentially, the addresses of the present lines which are scanned.

Communication line scanning device for a communication controller

The address generating device is provided for a communication line scanning device. The lines are connected to the scanning device through n line interface circuits, n varying in accordance with the network configuration. Each interface circuit can be connected to a various number of lines, for instance one line or k lines in a preferred embodiment, and comprises means for providing to the address generating device, a presence indicating signal indicating that it is plugged and a signal indicating the number of the lines connected thereto. A first logic circuit receives the presence indicating signals as inputs and generates on its outputs the address bits of the last present interface circuit to be scanned. A first counter able to count in binary mode up to n-1 is incremented by an increment pulse provided by a clock on each period assigned to the scanning of a line. This counter outputs the address bits of the successive interface circuits. A comparator compares the address bits so generated and the address bits of the last present interface circuit to be scanned and outputs a reset signal when these bits are equal.

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Antibes, France

Andre Masclet