The University of British Columbia

Pmc-Sierra, Inc.

Vector 12 Corporation

Andre Ivanov

Brian D Gerson

Curtis Brian Lapadat

Alan A Lowe

Yuejian Wu

Sassan Tabatabaei

Kamal Dalmia

A time to digital converter (TDC) has a pair of digital oscillators. The periods of the oscillators differ by T . The oscillators are triggered by START and STOP pulses. A counter counts a number of pulses until reference points on the signals output by the oscillators coincide. Measurements may be made using a dual resolution method. Intrinsic jitter of the TDC can be determined by comparing sets of measurements in which the switch in resolutions is made at different points. A range extender circuit may be provided to extend a valid measurement range of the TDC.

High resolution time-to-digital converter

A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.

Built-in test scheme for a jitter tolerance test of a clock and data

A low power consumption system for monitoring time of use of appliance incorporates a controller and a temperature sensor that is activated by the controller at intervals of X minutes to determine the temperature of the sensor. The sensed temperature is then compared with a threshold temperature and a counter is turned ON to accumulate time if the sensed temperature is at the desired level or turned OFF when the sensed temperature is not in the desired range. The counter remains in its ON or OFF position until the sensed temperature causes the counter to shift to the opposite position to the one it is in at that time. The counter receives oscillations from the oscillator which is continuously operating and only counts those oscillations when the counter is set in the ON position.

Time monitoring appliance

A method of testing a digital integrated circuit for faults. A plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n are established to define a test sequence. A set of m references r.sub.1, r.sub.2, . . . , r.sub.m are predefined, corresponding to the signatures which the circuit would produce at the corresponding check points in the absence of any faults. A test sequence is applied to the circuit and an output signature s.sub.i is derived from the circuit at the corresponding check point l.sub.i. The output signature is compared with each member of the set of references. The circuit is declared 'good' if the signature matches at least one member of the set of references, or 'bad' if a signature matches no members of the set of references. Testing proceeds in similar fashion at the next check point, until the circuit has been tested at all check points.

Growing community of inventors

Richmond, CA, United States of America

Andre Ivanov