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Andre Helen

Michel Servel

Alain M Thomas

A memory arrangement for temporary data storage of the FIFO type includes a random access memory associated with an input buffer register and two output buffer registers. The registers may consist of transparent flip-flops. The control system for the arrangement is provided for authorizing reading out from the output register at any time independently of the writing times in the random access memory and for causing reading out from the random access memory in response to an indication that the first output register is empty. A priority input of said control system makes it possible to interrupt a reading or writing operation when a request for the other operation is received. The control system has means for detecting full condition and empty condition of the FIFO. The control system further includes a handling logic for the output registers. That handling logic has two flip-flops which respectfully represent the presence of data in the two output registers and a circuit for setting the first flip-flop in response to loading of the first output register during an internal reading cycle in the random access memory and a circuit for emptying the second register and resetting the second flip-flop in response to a reading request by a user.

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Louannec - Perros Guirec, France

Andre Helen