Skyworks Solutions, Inc.

Conexant Systems, Inc.

Andre G Metzger

Peter J Zampardi

Shiaw Wen Chang

Ziv Alon

Bin Li

Kai Hay Kwok

Cristian Cismaru

Thomas L Fowler

Guoliang Zhou

Amish Naik

Charles E Chang

Aleksey A Lyalin

Michael L Hageman

Peter Phu Tran

Terry J Shie

Keith Nellis

Grant Small

Anise M Azizad

Kerry Burger

Small Grant

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having increased collector thickness for improved ruggedness. In some embodiments, the collector thickness can be above 1.1 microns. The collector can have at least one doping concentration grading. The collector can have a high doping concentration at a junction between the collector and the sub-collector, such as at the high end of the grading. In some embodiments, the high doping concentration can be above about 9×10cm. The collector can include a region with high doping concentration adjacent the base. The collector can include a discontinuity in the doping concentration, such as at the low end of the grading. Such bipolar transistors can be implemented, for example, in power amplifiers.

Bipolar transistor having collector with doping concentration grading

Bipolar transistor having collector with doping concentration discontinuity

A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage can be applied to the back gate of the FET.

Tunable device having a FET integrated with a BJT

A circuit for biasing a gallium arsenide (GaAs) power amplifier includes a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system, a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage.

Circuit and method for biasing a gallium arsenide (GaAs) power amplifier

A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.

Continuous tunable LC resonator using a FET as a varactor

A circuit for generating a reference voltage includes a first transistor configured to receive a reference system voltage, the first transistor configured as a current source, the first transistor configured to provide a current independent of the system voltage, a plurality of diode devices configured to receive the current provided by the first transistor, and a second transistor associated with the plurality of diode devices, the second transistor configured to compensate for process variations in the first transistor, such that the plurality of diode devices provides a reference voltage that is at least partially compensated for the process variations.

Circuit and method for generating a reference voltage

A method and apparatus for biasing an amplifying device whereby the bias current tracks the input power or the power level of a control signal to thereby efficiently match the bias current with needs of the amplifying device. This method and apparatus overcomes the drawbacks of the prior art by biasing, not for maximum output power, but for the power level of the input signal or the control signal. In one embodiment a current conditioner operates in connection with the self adjusting biasing circuit to scale or adjust, potentially on an exponential basis, the biasing current for one or more amplifier stages. A cancellation current source may be configured within the bias circuit to cancel unneeded current to further minimize current consumption.

Bias control for reducing amplifier power consumption and maintaining linearity

According to one exemplary embodiment, a circuit arrangement includes a power amplifier configured to receive an RF input signal. The circuit arrangement further includes a control circuit configured to receive and convert the RF input signal to an output DC voltage. The control circuit includes a voltage amplifier coupled to a peak detector circuit, where the peak detector circuit outputs the output DC voltage. The circuit arrangement further includes an analog control bias circuit coupling the output DC voltage to a bias input of the power amplifier. The output DC voltage causes the power amplifier to have a quiescent current that increases in a way that is substantially logarithmic with respect to the amplitude of the RF input signal. An increase in the RF input power can cause a substantially linear increase in the output DC voltage, where the RF input power is measured in dBm.

Circuit for controlling power amplifier quiescent current

Quiescent current control circuit for power amplifiers

A high-isolation, low-power high-speed multiplexer circuit suitably includes a buffer stage and a current steering tree stage. By employing common select lines for both stages of the circuit, both the input buffer and the deselected channel provide cumulative isolation for the deselected channels.

High isolation, low power high speed multiplexer circuit

Growing community of inventors

Newbury Park, CA, United States of America

Andre G Metzger