Zilog, Inc.

Andre B Walker

Tom S Wei

Elisabeth Ekman

Victor So

Stephen Clark

A microcontroller power management system wherein the voltage of a power supply is monitored and the microcontroller central processing unit ('CPU') receives an interrupt signal when the supply voltage falls below a predetermined level. The CPU monitors the duration of the low voltage condition and switches into a sleep mode, after storing any data in its registers that are not maintained in the sleep mode, when that duration exceeds a fixed limit that indicates more than a temporary power glitch is being experienced. If only a short power glitch, the CPU continues normal operation. A large capacitor connected to the power supply input to the microcontroller provides enough energy for the microcontroller to operate normally during short glitches and to operate in a sleep mode for a considerable time, thereby maintaining data in CMOS static RAM until power is restored. This is particularly useful for battery operated systems, responding to both a low battery voltage condition and to a complete loss of power during battery replacement.

Power supply interruption detection and response system for a

In an oscillator circuit, a high gain, high power driver is placed in parallel with a standard low gain, low power driver for driving the oscillator output. A control signal is derived from the output of the oscillator circuit and fed back to control the high gain driver. After the circuit output has achieved stable oscillations for a predetermined time period, the high gain driver is turned off. Employment of the high gain driver ensures high start-up ability. The overall power consumption remains low since the high gain driver is turned off after stable oscillations have been achieved.

Low power oscillator with high start-up ability

A CMOS N-channel, open-drain, pull-down buffer circuit is capable of pulling down voltages on an external pad in excess of the breakdown voltage of the individual N-channel field effect transistors in the buffer circuit. The circuit may be fabricated as part of a CMOS interated circuit in an industrial standard 1.5 microns CMOS process. The higher voltage acceptance is effected by using two open-drain N-transistors in series such that the external voltage is divided among the two transistors. A parallel high voltage circuit to the external pad can be independently optimized to provide a lower impedance path and a higher endurance for electrostatic discharge. While the two-transistor voltage divider exposes one of the transistor' gate to ESD via another external terminal, enhanced ESD protection is effected by having a resistor in series between the gate and the external terminal.

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Los Gatos, CA, United States of America

Andre B Walker