Xilinx, Inc.

Anders T Dejenfelt

Qi Lin

Robert A Olah

Kameswara K Rao

Michael G Ahrens

David Kuan-Yu Liu

George H Simmons

Sunhom Paak

Sholeh Diba

Phillip A Young

Tomoyuki Furuhata

Diane M Hoffstetter

Cyrus Chang

A nonvolatile EEPROM cell having a double poly arrangement provides stored data without sense amplifiers, thereby reducing power requirements. The EEPROM cell has a floating gate in a first poly layer, and a control gate overlapping the floating gate in a second poly layer. This configuration allows for an area-efficient layout that is easily shrinkable as compared to prior art memory cells. In addition, stacking the control and floating gates results in higher capacitive coupling. The EEPROM cell also includes an access gate, a tunnel capacitor, and at least one inverter. In some embodiments, the EEPROM cell can be advantageously used to configure programmable logic without need for a conloading step.

Shrinkable and highly coupled double poly EEPROM with inverter

An EEPROM memory cell array architecture ( ) that substantially eliminates leakage current to allow for reading memory cells ( ) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor ( ). On one embodiment, the ground transistor ( ) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor ( ) and the memory cell&equals;s read transistor ( ). In another embodiment, the ground transistor ( ) is a low voltage transistor controlled by a separate low voltage control signal.

EEPROM memory cell array architecture for substantially eliminating leakage current

A method is provided to increase the speed of a non-volatile memory transistor by increasing the read channel current in the non-volatile memory transistor. This increase in speed is accomplished without increasing the V voltage supply source or decreasing the channel length of the non-volatile memory transistor. The increase in read channel current is accomplished by applying a low voltage to the substrate region of the non-volatile memory transistor, while grounding the source of the non-volatile memory transistor. If the non-volatile memory transistor is located in an array, the low voltage is applied to the sources and drains of non-volatile memory transistors on unselected bit lines to inhibit junction leakage channel current from these unselected non-volatile memory transistors.

Method for enhancement of non-volatile memory cell read current

A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

Method to implement flash memory

A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Method of forming a two transistor flash EPROM cell

Method for operating flash memory

Two transistor flash EPROM cell

A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor. The first well region, the second well region, the non-volatile memory transistor and the access transistor are biased such that electrons are transferred from the first well region to a floating gate of the non-volatile memory transistor by Fowler-Nordheim tunneling during an erase mode, and electrons are transferred from the floating gate of the non-volatile memory transistor through the access transistor by Fowler-Nordheim tunneling during a program mode. None of the biasing voltages exceed 12 Volts, thereby enabling the flash EEPROM cell to operate in a 3.3 Volt system. In one embodiment, an array of flash EEPROM cells are fabricated in the second well region.

Two transistor flash EEprom cell and method of operating same

A programmable logic cell which includes a first transistor having a first conductivity type, and a second transistor having a second conductivity type, opposite the first conductivity type. The first transistor is coupled in series between a first voltage supply terminal and an output terminal, while the second transistor is coupled in series between a second voltage supply terminal and the output terminal. The first and second transistors share a common floating gate and a common control gate, which extends over the common floating gate. The floating gate has substantially the same layout as the control gate. When the floating gate is programmed to store charge of a first polarity, the programmable logic cell enters a non-volatile first state and provides an output signal having a first logic state. When the floating gate is programmed to store charge of a second polarity, the programmable logic cell enters a non-volatile second state and provides an output signal having a second logic state. When the floating gate is programmed to store a neutral charge, the programmable logic cell enters a third state in which the programmable logic cell provides an output signal representative of a predetermined logic function in response to one or more input signals. This logic function can be, for example, an inverter function, a logical NAND function, or a logical NOR function. The output terminal of the programmable logic cell can be coupled to a pass transistor of a programmable interconnect structure or to a configurable logic block of a field programmable gate array.

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Palo Alto, CA, United States of America

Anders T Dejenfelt