Nordic Semiconductor Asa

Anders Nore

Ronan Barzic

Joar Rusten

Vegard Endresen

Berend Dekens

Frank Aune

Per-Carsten Skoglund

Rolf Ambühl

Steffen Wiken

Fredrik Jacobsen Fagerheim

Nils Strøm

A radio receiver apparatus comprises radio circuitry for receiving a sequence of radio data packets, transmitted at regular intervals, wherein the sequence of radio data packets encodes a digital audio stream and each radio data packet encodes a respective number of audio samples from the digital audio stream. The apparatus also comprises a digital audio interface for outputting audio samples from the received digital audio stream, a controllable oscillator arranged to control an output rate at which the audio samples are output from the digital audio interface, and a timer. The apparatus also comprises control logic, configured to use the timer to measure an interval between receiving each of a pair of the radio data packets, and to control the oscillator to vary the output rate incrementally, in a number of steps, while outputting the audio samples from one radio data packet. The number of steps, or the size of each step, or both, depends on the measured interval.

Radio apparatus for communicating digital audio streams

A microcontroller system comprising a master microcontroller unit, a further module and a general purpose input/output. In a first state the general purpose input/output is controlled by the master microcontroller unit and in a second state the general purpose input/output is controlled by the further module. The master microcontroller unit is arranged to transmit a selection signal which changes the state of the general purpose input/output.

Microcontroller system with gpios

An integrated-circuit device comprises a processor, a peripheral component, a bus system, connected to the processor and to the peripheral component, and configured to carry bus transactions; and hardware filter logic. The bus system is configured to carry security-state signals for distinguishing between secure and non-secure bus transactions. The peripheral component comprises a register interface, accessible over the bus system, and comprising a hardware register and a direct-memory-access (DMA) controller for initiating bus transactions on the bus system. The peripheral component supports a secure-in-and-non-secure-out state in which the hardware filter logic is configured to prevent non-secure bus transactions from accessing the hardware register of the peripheral component, but to allow secure bus transactions to access the peripheral component. The peripheral component is configured to allow an incoming secure bus transaction to access the hardware register and to initiate a bus transaction as non-secure.

Peripheral access on a secure-aware bus system

An integrated-circuit device comprises a bus system connected to a processor, a plurality of peripherals, each connected to the bus system, hardware filter logic; and a peripheral interconnect system, separate from the bus system and connected to the peripherals. For each peripheral, the hardware filter logic stores a respective value determining whether the peripheral is in a secure state. The peripheral interconnect system provides a set of one or more channels for signalling events between peripherals. At least one channel is a secure channel or is configurable to be a secure channel. The peripheral interconnect system is configured to allow an event signal from a peripheral in the secure state to be sent over a secure channel and to prevent an event signal from a peripheral that is not in the secure state from being sent over the secure channel.

Secure peripheral interconnect

A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

Inter-processor communication

An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response. The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.

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Trondheim, Norway

Anders Nore