Huawei Technologies Co., Limited

Anders Jakobsson

Christian Grewing

Anders Emericks

Bingxin Li

Ola Pettersson

A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.

Phase interpolator and interpolating method

A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal SDLYat a first point tin time and a second delay signal SDLYat a second point in time t. The sampler module is configured to provide a first sample Sof the oscillator output signal SOUT at the first point in time tand a second sample Sof the oscillator output signal SOUT at the second point in time t. The interpolator is configured to provide a sampler signal SSAMPL by interpolating the first sample Sand the second sample S. The voltage controlled oscillator is configured to control the oscillator output signal SOUT based on the sampler signal SSAMPL.

Sub-sampling phase-locked loop

A sub-sampling phase-locked loop is described, which comprises a digital-to-time converter, a sampler module, an interpolator, and a voltage controlled oscillator. The digital-to-time converter is configured to provide a first delay signal (S) at a first point (t) in time and a second delay signal (S) at a second point in time (t). The sampler module is configured to provide a first sample (S) of the oscillator output signal (S) at the first point in time (t) and a second sample (S) of the oscillator output signal (S) at the second point in time (t). The interpolator is configured to provide a sampler signal (S) by interpolating the first sample (S) and the second sample (S). The voltage controlled oscillator is configured to control the oscillator output signal (S) based on the sampler signal (S).

An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.

Spur suppression in a phase-locked loop

A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Method and apparatus for generating a carrier frequency signal

A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.

System and method for calibrating output frequency in phase locked loop

A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) () comprising a voltage controlled oscillator (VCO) () controlled by means of a tuning voltage (V) is disclosed. An embodiment of the invention compares the VCO tuning voltage (V) to a low threshold voltage (V) and a high threshold voltage (V), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL () forces the tuning voltage (V) towards the high threshold voltage (V) when the low threshold voltage (V) is reached, and offsetting the divider value such that said PLL () forces the tuning voltage (V) towards the low threshold voltage (V) when the high threshold voltage (V) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL ().

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Kista, Sweden

Anders Jakobsson