Micron Technology Incorporated

Aptina Imaging Corporation

Photobit Corporation

Anders Andersson

Sandor L Barna

Alexander I Krymski

Nikolai E Bock

Barmak Mansoorian

Eric R Fossum

Daniel A Van Blerkom

David B Schick

Abe Kotlyar

Daniel Van Berkom

Daniel Van Blerkom

Abraham Kotlyar

An image sensor includes pixels each of which is designed to transfer charge, accumulated in a photoactive region of the pixel during a first period, through a second active region of the pixel to a power supply node, and to transfer charge, accumulated in the photoactive region during a second period, through the second active region to a sense node in the pixel. Passing charge through the second active region prior to transferring it either to the power supply node or the sense node can help reduce fixed pattern noise. The image sensor can be operated in snap-shot mode.

Active pixel sensor with reduced fixed pattern noise

Imaging sensors having dual-port for digital readout to pipeline readout processes of two different groups of pixels.

Semiconductor imaging sensor array devices with dual-port digital readout

An active pixel sensor (APS) includes an array of individually addressable APS cells ad a pixel readout structure that includes an amplifier. The amplifier may have a two-branched structure and provide a gain of one or higher. Additional switches may be provided in the pixels to provide protection for pixel output transistors from voltage changes in the column line. Structure may also be provided for optional gain selection in the amplifier.

Active pixel sensor (APS) readout structure with amplification

Active pixel sensor with reduced fixed pattern noise using two active regions

A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at least one set of second decoders, each set being associated with respective first decoder. The first decoder decodes a first portion of an address representing a desired pixel array column and, depending on the results of the first decoding operation, selectively enables the associated second decoder set which decodes a second portion of the address to select a column line.

CMOS imager decoder structure

A circuit having a plurality of circuit blocks formed on a semiconductor substrate is disclosed. The circuit blocks are stitched together by appropriately connecting input and output lines of the plurality of circuit blocks. The circuit also includes connecting circuits coupled to the plurality of circuit blocks. The connecting circuits provide low voltage drop across boundaries where the plurality of circuit blocks are stitched together.

Stitched circuits larger than the maximum reticle size in sub-micron process

The present invention is a system for assigning unique addresses to multiple devices attached to an I C bus. When multiple devices share the same I C address, the master device is unable to communicate with each device individually. Therefore, a circuit enable input is created to individually activate each device. Once a device is activated, the master device may communicate to the device a unique I C bus address, after which the activated device only responds to the new address. Each device initially sharing the same address is activated individually until all devices have been assigned a unique address.

Multi-chip addressing for the I2C bus

A technique and structure for simplifying the stitching process is disclosed. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout method for a row/column decoder that reduces the number of blocks when stitching.

Layout technique for semiconductor processing using stitching

A ping-pong A/D converter which produces an output at alternate times on alternate memories.

Growing community of inventors

Pasadena, CA, United States of America

Anders Andersson