Nxp B.v.

Koninklijke Philips Corporation N.V.

Taiwan Semiconductor Manufacturing Comp. Ltd.

U.S. Philips Corporation

Nexperia B.v.

Trixell

Koninklijke Philips Electronics N.v.

Anco Heringa

Jan Willem Slotboom

Jan Sonsky

Tony Vanhoucke

Evelyne Gridelet

Viet Thanh Dinh

Erwin Hijzen

Dirk Klaassen

Roel Daamen

Radu Surdeanu

Adrianus W Ludikhuize

Raymond J E Hueting

Victor Zieren

Johannes Donkers

Erik Jan Lous

Liang Yan

Ronald Dekker

Peter G Steeneken

Thomas Frach

Klaus Reimann

Olaf Wunnicke

Hendrik Johannes Bergveld

Rob Van Dalen

Robert Hendrikus Margaretha Van Veldhoven

Hans-Martin Ritter

Robert Van Veldhoven

Prabhat Agarwal

Wibo Daniel Van Noort

Gerhard Koops

Gilberto Curatola

Henricus Godefridus Rafael Maas

Maarten Jacobus Swanenberg

Wolfgang Schnitt

Markus Mueller

Henricus G R Maas

Jan Claes

Holger Schligtenhorst

Ivan Mitkov Zahariev

Albertus Theodorus Maria Van De Goor

Luc Van Dijk

Wilhelmus Cornelis Maria Peters

Philippe Meunier-Bellard

Alessandro Ferrara

Joost Willem Christiaan Veltkamp

Phillippe Meunier-Bellard

Paulus J T Eggenkamp

Priscilla W M Boos

Raymond Van Roijen

Johannes Hendrik Hermanus Alexius Egbers

Godefridus Antonius Maria Hurxk

Viet Dinh

Johannes Josephus Theodorus Martinus Donkers

Boni Kofi Boksteen

Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

Transistor amplifier circuit and integrated circuit

The disclosure relates to bipolar transistor devices and a method of fabricating the same. The device comprises a field plate, in an isolation region adjacent to a base-collector junction of said active region. The isolation region comprises a gate terminal arranged to be biased independently of a collector, base or emitter terminal of said transistor.

Bipolar transistor device and method of fabrication

A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

Semiconductor device having control conductors

Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode.

Apparatuses and methods including a superjunction transistor

An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Semiconductor device with an integrated heat sink array

A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit.

Semiconductor device and circuit with dynamic control of electric field

Semiconductor device with heat sinks

Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate () to form a buried region () therein; forming a halo implant () using an impurity of a second type and a shallow implant () using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (); forming, adjacent to the halo implant (), a further implant () using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections () to the further implant (), the shallow implant () and the buried region () allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.

IC and IC manufacturing method

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having an AlGaN layer on a GaN layer. The device also includes first contact and a second contact. The average thickness of the AlGaN layer varies between the first contact and the second contact, for modulating the density of an electron gas in the GaN layer between the first contact and the second contact.

Semiconductor device

An ESD protection circuit comprises a series connection of at least two protection components between a signal line to be protected and a return line (e.g. ground), comprising a first protection component connected to the signal line and a second protection component connected to the ground line. They are connected with opposite polarity so that when one conducts in forward direction the other conducts in reverse breakdown mode. A bias voltage source connects to the junction between the two protection components through a bias impedance. The use of the bias voltage enables the signal distortions resulting from the ESD protection circuit to be reduced.

ESD protection

A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base.

Bipolar transistor having laterally extending collector

Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

Field plate assisted resistance reduction in a semiconductor device

A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field.

Semiconductor magnetic field sensors

The invention provides a semiconductor device () for radiation detection, which comprises a substrate region () of a substrate semiconductor material, such as silicon, and a detection region () at a surface of the semiconductor device (), in which detection region () charge carriers of a first conductivity type, such as electrons, are generated and detected upon incidence of electromagnetic radiation (L) on the semiconductor device (). The semiconductor device () further comprises a barrier region () of a barrier semiconductor material or an isolation material, which barrier region () is an obstacle between the substrate region () and the detection region () for charge carriers that are generated in the substrate region () by penetration of ionizing radiation (X), such as X-rays, into the substrate region (). This way the invention provides a semiconductor device () for radiation detection in which the influence on the performance of the semiconductor device () of ionizing radiation (X), such as X-rays, that penetrates into the substrate region () is reduced.

Semiconductor device for radiation detection

A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.

Field-effect magnetic sensor

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Waalre, Netherlands

Anco Heringa