United Microelectronics Corp.

United Semiconductor Corp.

Anchor Chen

Gary Y Hong

Jing-Horng Gau

Chen-Chiu Hsue

Ming-Tzong Yang

Shu-Ya Chuang

Jhy-Jyi Sze

Sun-Chieh Chien

Ming-Tsung Tung

Hwi-Huang Chen

Chih-Hung Lin

Robin Lee

Jung-Ching Chen

Hsiu-Wen Huang

Shih-Ching Chen

Chin-Hung Liu

Jih-Wei Liou

Chien-Ming Lin

Jin-Horng Gau

Min-Tzong Yang

Jing-Horng Gan

Liang-Hua Lin

An image sensor and a manufacturing method thereof are provided. The image sensor includes a plurality of sensors, an inter-layer dielectric layer formed over the sensors, a first inter-metal dielectric layer formed over the inter-layer dielectric layer, and a plurality of first via walls formed in the first inter-metal dielectric layer, wherein each of the first via walls is formed around each of the sensors. In addition, the image sensor further includes a second inter-metal dielectric layer formed over the first inter-metal dielectric layer and a plurality of second via walls formed in the second inter-metal dielectric layer, wherein each of the second via walls is formed around each of the sensors. Therefore, the light leakage between different pixels and the problem of crosstalk are solved, and the spatial resolution and the photo sensitivity of the image sensor are enhanced.

Image sensor device and manufacturing method thereof

The invention is directed to a method for manufacturing a high voltage device. The method includes steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in the substrate. The second doped regions are located adjacent to both sides of the first doped region respectively, and the first doped region is separated from the second doped regions with an isolation region. A gate structure is formed on the substrate between the second doped regions and a source/drain region having the second doped region is formed in the substrate adjacent to both sides of the gate structure.

High voltage device

The invention is directed to a method for manufacturing a high voltage device. The method comprises steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in the substrate, wherein the second doped regions are located adjacent to both sides of the first doped region respectively, and the first doped region is separated from the second doped regions with an isolation region. A gate structure is formed on the substrate between the second doped regions and a source/drain region having the second doped region is formed in the substrate adjacent to both sides of the gate structure.

Method for forming high voltage device and semiconductor device

A bipolar junction transistor includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a semiconductor layer formed on a sidewall and a bottom of the opening and on a portion of the dielectric layer outside the opening, a spacer formed on the semiconductor layer to define a self-aligned emitter region in the opening, an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the semiconductor layer, and a salicide layer formed on the emitter conductivity layer and on the portion of the semiconductor layer extending outside the opening.

Bipolar junction transistor and fabricating method

A high-voltage device structure includes a high-voltage device disposed on a semiconductor substrate. The semiconductor includes an active region and an isolation region, and the high-voltage device is disposed in the active region. The high-voltage device structure includes a source diffusion region of a first conductive type, a drain region of the first conductive type, and a gate longer than the source diffusion region and the drain diffusion region so as to form spare regions on both sides of the gate. The isolation region is outside the active region and surrounds the active region. In the isolation region, an isolation ion implantation region of a second conductive type and an extended ion implantation region are disposed to prevent parasitic current from being generating between the source diffusion region and the drain diffusion region.

High-voltage device structure

A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Variable capacitor structure and method of manufacture

Variable capactor structure and method of manufacture

A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.

A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.

Method for fabricating a vertical bipolar junction transistor

A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

Fabrication of self-aligned bipolar transistor

A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor. Second heavily doped regions of the first conductivity type located in the first ion well at one side of the first dummy gate that is opposite to the first heavily doped region and at one side of the second dummy gate that is opposite to the first heavily doped region, the second heavily doped regions being electrically connected to each other and serving as a cathode of the PN junction varactor.

Junction varactor with high Q factor and wide tuning range

Variable capactor structure

A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

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Pingtung, Taiwan

Anchor Chen