Taiwan Semiconductor Manufacturing Comp. Ltd.

Anbiarshy Wu

Shin-Puu Jeng

Hsien-Wei Chen

Shang-Yun Hou

Shih-Hsun Hsu

Hao-Yi Tsai

Hsueh-Chung Chen

Chia-Lun Tsai

Shih-Cheng Chang

Benson Liu

A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.

Test structure for seal ring quality monitor

Fuse structures and integrated circuit devices are disclosed. An exemplary embodiment of a fuse structure comprises a first and second metal pads formed at different positions in a first dielectric layer and a conductive line formed in a second dielectric layer underlying the first dielectric layer, electrically connecting the first and second pad. The conductive line is formed with at least one first portion at an end thereof and a second portion connected with the first portion, wherein the width of the first portion is greater than the width of the second portion.

Fuse structures and integrated circuit devices

An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

Pad structure design with reduced density

Growing community of inventors

Chiayi, Taiwan

Anbiarshy Wu