International Business Machines Corporation

Anastasios A Katsetos

Fernando Jose Guarin

Stewart E Rauch, Iii

Ping-Chuan Wang

Eric Peter Solecky

Charles Neill Archie

Joseph M Lukaitis

Giuseppe La Rosa

Georgios A Vakas

Stephen P Boffoli

B B (Bob) Lawhorn

A method for measuring a dimension of a device includes receiving an image of a portion of the device, receiving a first offset value and a second offset value, processing the image to define a least one graph of a line of pixels, the at least one graph including the brightness level of each pixel in a line of pixels, identifying a location of a first peak and a second peak in the graph, defining a first exclusion area boundary, defining a second exclusion area boundary, setting the brightness level of the pixels between the first exclusion area boundary and the second exclusion area boundary to zero, identifying a first portion of the feature of interest and a second portion of the feature of interest, and measuring a distance between the first portion of the feature of interest and the second portion of the feature of interest.

Methods and systems involving measuring complex dimensions of silicon devices

A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current driver and a second pass-gate connected to a ground. The recovery circuit also has a recovery assembly or element and one or more contacts operatively connecting the recovery circuit to a wearout sensitive circuit or circuit element.

Method and circuit for element wearout recovery

A MOSFET test structure and associated electronics for rapidly heating the MOSFET gate oxide and for applying a stress voltage to the gate. The structure has at least one polysilicon gate with two spaced contacts that permit a heating current to flow through the gate thus rapidly raising the gate temperature to a desired level. External electronics permit applying a measured stress voltage to the gate. The structure is particularly useful in NBTI testing of p-MOSFETs.

Method and structure for in-line monitoring of negative bias temperature instability in field effect transistors

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Poughkeepsie, NY, United States of America

Anastasios A Katsetos