Lumileds LLC

Jds Uniphase Corporation

Anantharaman Vaidyanathan

Ronald Johannes Bonne

Tze Yang Hin

Robert Brainard

Sanjay M Thekdi

Srini Banna

Thomas Nguyen

David K Nakamoto

Jyoti Kiron Bhardwaj

Barthelemy Fondeur

David J Dougherty

Hiroaki Yamada

Zi-Wen Dong

Anca L Sala

Erik W Egan

Niranjan Gopinathan

Yingchao Yan

Suresh Ramalingam

Douglas E Crafts

Kenzo Ishida

James F Farrell

Steven M Swain

David J Chapman

Mark Brian Farrelly

Duncan Harwood

Tom Truong

Ian Hutagalung

Systems are described. A system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane. The substrate has a top surface, a bottom surface and side surfaces. At least one bond pad is provided on the bottom surface of the substrate. A metal layer is provided on the bottom surface of the substrate and the bottom surface of the silicon backplane and has a first portion electrically and thermally coupled to the bottom surface of the silicon backplane in a central region and second portions that extend between a perimeter region of the silicon backplane and the at least one bond pad. An array of metal connectors is provided on the top surface of the silicon backplane.

Fan out structure for light-emitting diode (LED) device and lighting system

Methods of manufacturing a system are described. A method includes attaching a silicon backplane to a carrier and molding the silicon backplane on the carrier such that a molding material surrounds side surfaces of the silicon backplane to form a structure comprising a substrate with an embedded silicon backplane. The structure has a first surface opposite the carrier, a second surface adjacent the carrier, and side surfaces. At least one via is formed through the molding material and filled with a metal material. A metal layer is formed on a central region of the first surface of the structure. Redistribution layers are formed on the first surface of the structure adjacent the metal layer.

LED lighting systems and vehicle headlamp systems are described. An LED lighting system includes a silicon backplane having a top surface, a bottom surface, and side surfaces and a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces. First redistribution layers are provided on the top surface of the silicon backplane and the top surface of the substrate. Second redistribution layers are provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layers and the second redistribution layers and is filled with a metal material.

The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.

Planar circuit optimization

The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all. Segmented trenches appear to allow for the lowest stress on the two waveguide arms of all the cases including no trench and trenched devices.

Planar lightwave circuit variable optical attenuator

A planar lightwave circuit includes at least one optical waveguide core, and at least one feature proximate the core having a stress-engineered property to balance stress and therefore minimize birefringence affecting the core. A protective passivation layer is formed over the core and the feature to be substantially non-interfering with the balanced stress provided by the feature. The stress balancing feature may be an overcladding layer formed over the core, doped to have a coefficient of thermal expansion approximately matched to that of an underlying substrate, to symmetrically distribute stress in an undercladding between the overcladding and the substrate, away from the core. The protective passivation layer is formed to have a coefficient of thermal expansion approximately matched to that of the overcladding. In one exemplary embodiment, the passivation layer is formed from silicon nitride. Related concepts of stress release grooves, and core overetching, are also disclosed.

Waveguide stress engineering and compatible passivation in planar lightwave circuits

A planar lightwave circuit includes an arrayed waveguide grating (AWG), with input and output waveguides, partially curved array waveguides with respective length differences, and planar waveguide regions for focusing optical energy between the input/output and array waveguides. Optimal waveguide widths and spacing along the planar waveguide region facets are disclosed, which are largely determinative of AWG size and optical performance. Also disclosed are optimal cross-sectional waveguide dimensions (e.g., width and height); modified index of refraction difference between the waveguide core and cladding regions; and optimal array waveguide lengths, path length differences, and free spectral range. These features, especially when combined with advanced fiber attachment, passivation and packaging techniques, result in high-yield, high-performance AWGs (both gaussian and flattop versions).

Compact, low insertion loss, high yield arrayed waveguide grating

Growing community of inventors

San Jose, CA, United States of America

Anantharaman Vaidyanathan