Intel Corporation

Ananthan Ayyasamy

Debendra Das Sharma

Robert G Blankenship

Mahesh U Wagh

Zuoguo Wu

Robert J Safranek

Gerald S Pasdast

Xiaobei Li

Lidia Warnes

Hugh Wilkinson

Donald L Faw

Douglas Carrigan

Jain Philip

Ajith Prasad

Ankit Patel

Paritosh Joshi

Xiaobel Li

Zuoguo J Wu

Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.

Memory access tracing

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Multichip package link

In a method of allocating a shared resource among a plurality of competing applicants, a share of the resource allocated to one of the applicants is limited on the basis of a current proportion of the resource allocated to the applicant and a total of respective shares of the resource currently allocated to all of the applicants.

Methods and apparatus for asserting flow control at input ports of a shared-memory switch

Growing community of inventors

Beaverton, OR, United States of America

Ananthan Ayyasamy