Western Digital Technologies, Inc.

Anantha Raman Krishnan

Kent Douglas Anderson

Shafa Dahandeh

Guangming Lu

Majid Nemati Anaraki

Shayan Srinivasa Garani

Yiming Chen

Kasra Vakilinia

Andrew John Tomlin

David W Wheelock

Aravind Raghunathan

An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. Bit patterns provided by multiple reads of reference memory locations can be counted and used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.

Method and system for decoding data based on association of first memory location and second memory location

Soft-decision input generation for data storage systems

A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

System and method for decoding iterations and dynamic scaling

A data storage device is disclosed comprising a storage medium. Input data is encoded according to at least one channel code constraint to generate first data and second data. The first data is encoded into a first codeword, and the second data is encoded into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium.

Data storage device encoding and interleaving codewords to improve trellis sequence detection

System and method for dynamic scaling of LDPC decoder in a solid state drive

In some embodiments of the present invention, a data storage device includes a controller and a memory. The data storage device further includes an LDPC encoder and decoder, with the decoder implementing a dynamic precision-rescaling technique for improving performance. In one embodiment, the technique works by rescaling the binary representations of the input log-likelihood ratios (LLRs) and messages upon activation of decoder-state-based triggers. Various triggering functions are introduced, e.g., checking if the number of output LLRs smaller than a certain limit crosses a threshold, checking if the weight of a syndrome crosses a threshold, etc. This technique offers an improvement in the performance of the decoder.

In one embodiment, an electronic system includes a decoder configured to decode an encoded data unit using multiple variable nodes and multiple check nodes to perform a low-density parity check (LDPC) decoding process. The encoded data unit can be received from a solid-state memory array. As part of performing the LDPC decoding process, the decoder can (i) convert reliability information representing first non-binary values to reliability information representing first binary values, (ii) determine reliability information representing second binary values using the reliability information representing first binary values, and (iii) convert the reliability information representing the second binary values to reliability information representing second non-binary values.

Non-binary LDPC decoder using binary subgroup processing

Data storage systems may include a solid-state memory array configured to store encoded data units and a controller configured to decode the encoded data units. Decoding the encoded data units may include updating a check node of a plurality of check nodes associated with a parity check matrix by identifying first and second sets of variable nodes in a plurality of variable nodes associated in the parity check matrix with the check node and constructing a trellis based on the second set of variable nodes. The trellis may be used to determine a message and, based at least in part on the message, a first set of messages to be sent from the check node to the first set of variable nodes may be determined. A second set of messages to be sent from the check node to each variable node in the second set of variable nodes also may be determined.

Non-binary low-density parity check (LDPC) decoding using trellis maximization

A reader failover system and method are described for a data storage system. At least two reader systems, including a first reader element and a second reader element, situated on the same head, are employed to read a magnetic storage medium. In an aspect, the head is a two-dimensional magnetic recording (TDMR) head. Control circuitry detects when the first reader system provides less than a predetermined performance or fails, and thereafter causes the second reader system, but not the first reader system, to read the magnetic storage medium. In an aspect, a buffer stores a first reader element signal until the control circuitry detects whether or not the first reader element provides less than a predetermined performance or fails. In an aspect, when a reader element fails, data recovery is performed, and all of, or a majority of, the media continues to be readable, improving the data storage system robustness.

Read failover method and apparatus for a data storage system

A data storage system configured to adaptively code data and related methods are disclosed. In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller includes a channel monitor that determines the quality of read signals from the pages when they are read, and provides adjustment metrics to aid in the selection of a code rate, such as a code rate for a low-density parity-check (LDPC) code. In this way, the code rate used for data encoding can be dynamically adjusted to accommodate degradation of the non-volatile memory array over its useable life.

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Irvine, CA, United States of America

Anantha Raman Krishnan