Cypress Semiconductor Corporation

Rodel Inc.

Rodel Holdings, Inc.

Advanced Micro Devices Corporation

Anantha R Sethuraman

Lee Melbourne Cook

Jiun-Fang Wang

William W C Koutny, Jr

Sharath D Hosali

Christopher A Seams

Michael R Oliver

Huey-Ming Wang

Guangwei Wu

William W Koutny, Jr

The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.

Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect

The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures

The present invention advantageously provides a method and apparatus for polishing a semiconductor topography by applying a liquid which is void of particles between the topography and an abrasive polishing pad surface. The semiconductor topography is rotated relative to the polishing surface to polish elevationally raised regions of the topography. The particles are fixed within the polishing surface which may comprise a polymeric material. In one embodiment, the liquid may comprise water diluted with acid. If the liquid is adjusted to have a pH between 6.0 and 7.0, the polishing process may be used to remove a silicon dioxide layer from the topography at a faster rate than a silicon nitride layer residing beneath the oxide layer. Alternately, a metal may be selectively removed from above an oxide layer if the polishing liquid has a pH between 2.0 and 5.0. In another embodiment, the liquid may be deionized water. The water does not react with the material being polished. The polishing pad is made of a non-deformable material, and thus does not conform to the elevationally disparate semiconductor topography. Therefore, elevationally raised regions of the topography are removed at a faster rate than elevationally recessed regions.

Employing an acidic liquid and an abrasive surface to polish a semiconductor topography

The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxidant to the topography. According to an embodiment, a semiconductor topography is polished by a fixed-abrasive process in which the topography is pressed face-down on a rotating polishing pad having particles embedded in the pad while a liquid absent of particulate matter is dispensed onto the pad. The particles may include, e.g., cerium oxide, cerium dioxide, &agr;alumina, &ggr;alumina, silicon dioxide, titanium oxide, chromium oxide, or zirconium oxide. A cleaning solution comprising either (a) an acid and a peroxide, e.g., hydrogen peroxide, or (b) an acid oxidant is applied to the semiconductor topography after the polishing process is completed. Examples of acids that may be used include, but are not limited to, sulfuric acid, hydrochloric acid, hydrobromic acid, hydrofluoric acid, formic acid, acetic acid, nitric acid, perchloric acid, perbromic acid, performic acid, phosphoric acid, and peracetic acid Advantageously, the cleaning solution effectively eliminates all or at least a significant portion of the particles on the semiconductor topography.

System for cleaning a surface of a dielectric material

A method is provided for polishing a composite comprised of silica and silicon nitride wherein a polishing composition is used comprising: an aqueous medium, abrasive particles, a surfactant, an organic polymer viscosity modifier which increases the viscosity of the composition, and a compound which complexes with the silica and silicon nitride wherein the complexing agent has two or more functional groups each having a dissociable proton, the functional groups being the same or different.

Composition and method for polishing a composite of silica and silicon nitride

A composition is provided for polishing a composite comprised of silica and silicon nitride comprising: an aqueous medium, abrasive particles, a surfactant, and a compound which complexes with the silica and silicon nitride wherein the complexing agent has two or more functional groups each having a dissociable proton, the functional groups being the same or different.

Composition and method for polishing a composite of silica and silicon

Composition for polishing a composite of silica and silicon nitride

A process is provided for polishing a composite comprised of an insulating layer, a metal and titanium in which the composite is polished in a standard polishing machine using an aqueous slurry comprising submicron abrasive particles, an iodate, and a peroxide. Another process is provided in which peroxide is added to the aqueous slurry only when a titanium or titanium nitride layer is being polished. Further the invention also comprises the addition of a base to the slurry stream exiting the polishing machine to bring the pH of the used slurry to about 7 or higher.

Method for polishing a composite comprising an insulator, a metal, and

The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxidant to the topography. According to an embodiment, a semiconductor topography is polished by a fixed-abrasive process in which the topography is pressed face-down on a rotating polishing pad having particles embedded in the pad while a liquid absent of particulate matter is dispensed onto the pad. The particles may include, e.g., cerium oxide, cerium dioxide, .alpha. alumina, .gamma. alumina, silicon dioxide, titanium oxide, chromium oxide, or zirconium oxide. A cleaning solution including either (a) an acid and a peroxide, e.g., hydrogen peroxide, or (b) an acid oxidant is applied to the semiconductor topography after the polishing process is completed. Examples of acids that may be used include, but are not limited to, sulfuric acid, hydrochloric acid, hydrobromic acid, hydrofluoric acid, formic acid, acetic acid, nitric acid, perchloric acid, perbromic acid, performic acid, phosphoric acid, and peracetic acid. Advantageously, the cleaning solution effectively eliminates all or at least a significant portion of the particles on the semiconductor topography.

Method for cleaning a surface of a dielectric material

An aqueous slurry is provided which is useful for the chemical-mechanical polishing of substrates containing titanium comprising: water, submicron abrasive particles, an oxidizing agent, and a combination of complexing agents comprising a phthalate compound and a compound which is a di- or tri-carboxylic acid with at least one hydroxyl group in an alpha position relative to one of the carboxyl groups.

Composition and method for polishing a composite comprising titanium

A composition is provided for polishing a composite comprised of silica and silicon nitride comprising: an aqueous medium, abrasive particles, a surfactant, and a compound which complexes with the silica and silicon nitride wherein the complexing agent has has two or more functional groups each having a dissociable proton, the functional groups being the same or different.

An aqueous slurry is provided for polishing or planarizing a work piece which contains a metal, the solids portion of said slurry being comprised of 1 to 50 percent by weight of submicron alpha-alumina, the remainder of the solids being of a substantially less abrasive composition chosen from the group consisting of aluminum hydroxides, gamma-alumina, delta-alumina, amorphous alumina, and amorphous silica. Also provided is a method for polishing the surface of a work piece which contains a metal wherein said aqueous slurry is used as the polishing composition during chemical-mechanical polishing.

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Fremont, CA, United States of America

Anantha R Sethuraman