Texas Instruments Corporation

Anant Shankar Kamath

Rakesh Hariharan

Mark Edward Wentroble

Thomas Dyer Bonifield

Byron Lovell Williams

John Kenneth Arch

Suvadip Banerjee

Raja Selvaraj

Divyasree J

Swaminathan Sankaran

Suzanne Mary Vining

Kumar Anurag Shrivastava

Xiong Li

Tarunvir Singh

Sreeram N S

Srijan Rastogi

Karthik Subburaj

Jayawardan Janardhanan

Siraj Akhtar

Prakash Easwaran

Mayank Garg

Vijayalakshmi Devarajan

Shailendra Kumar Baranwal

Roland Sperlich

Martin Staebler

Wesley Ray

Dushmantha Bandara Rajapaksha

Abhijeeth Aarey Premanath

Kishalay Datta

Vikas Kumar Thawani

Sadia Arefin Khan

Christopher Joseph Rodrigues

Robert Floyd Payne

Krishnaswamy Nagaraj

Yogesh Kumar Ramadass

Keith Edmund Kunz

Biman Chattopadhyay

Maurizio Granato

Sreeram Subramanyam Nasum

Amal Kumar Kundu

Rupak Ghayal

Sujoy Chakravarty

Gaurav Chandra

Alan Stephen Bass

Bharath Kumar Singareddy

Shrinivasan Jaganathan

Sudheer Kumar Vemulapalli

Ujwal Radhakrishna

Vikas Kumar Sinha

Prajkta Vyavahare

Kashyap Jayendra Barot

Vinod Kuniganahalli Rai

Anandha Ruban Tiruchengode Tirumurugga Bupathi

Soumi Paul

Sundarasiva Rao Giduturi

Sriram Ramadoss

Shivaprakash Halagur

Rr Manikandan

Kanteti Amar

Gurumurti Kailaschandra Avhad

Prajwala P

Prajwala Puttappa

Yihuang Lin

Shubham Panjrath

Kevin Paul Herring

Vighnesh Rudra Das

Birman Chattopadhyay

Gopal Krishna Nayak

Sameer Raghavendra Joshi

Mithun Guddethota Neelakant

Subhash Yekanath Pai

Vivekkumar Ramanlal Vadodariya

In an example, a method of operating a repeater having an isolation barrier to isolate a host side of the repeater from a peripheral side of the repeater, the repeater operable to be coupled to a universal serial bus (USB), includes causing the host side to enter into a suspend mode. The method also includes, responsive to entering the suspend mode, disabling a host isolation transceiver at the host side. The method includes periodically enabling the host isolation transceiver to transmit a data signal from the host side to the peripheral side. The method includes exiting the suspend mode. The method also includes enabling the host isolation transceiver.

USB suspend mode in isolated USB repeater

Described embodiments include a voltage level shifter with a first driver having an input that receives a first signal, an output, a positive supply terminal coupled to a first supply terminal, and a negative supply terminal coupled to a second supply terminal. A transistor has first and second current terminals and a first control terminal. The first current terminal is coupled to the first driver output, and the first control terminal is adapted to be coupled to a low-side drive transistor control terminal. A second driver has an input coupled to the second current terminal, an output, a positive supply terminal coupled to a third supply terminal, and a negative supply terminal coupled to ground. The second driver provides a second signal at the second driver output. A voltage at the third supply terminal is less than 10% of a voltage at the first supply terminal.

Level shifter for high voltage driver

Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Rejection of end-of-packet dribble in high speed universal serial bus repeaters

A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

Multi-channel digital isolator with integrated configurable pulse width modulation interlock protection

In described examples, a converter circuit includes a primary-side ground, a current sensor, a control signal generator, first and second control switches, and a transformer with a center-tapped primary-side coil. A first terminal of the first control switch is coupled to a first terminal of the coil and a first input of the current sensor. A first terminal of the second control switch is coupled to a second terminal of the coil and a second input of the current sensor. Second terminals of the first and second control switches are coupled to ground. The control signal generator closes the first control switch and opens the second control switch in a first phase; opens the first control switch and closes the second control switch in a second phase that alternates with the first phase; and adjusts first phase duration in response to current sensor output, without changing converter period duration.

Push-pull converter with saturation prevention

A circuit includes a supply circuit having an input and an output. The supply circuit includes: a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the output of the supply circuit; a switch having a first terminal, a second terminal, and a control terminal, the first terminal of the switch coupled to the input of the supply circuit, the second terminal of the switch coupled to the output of the supply circuit; and a controller coupled to the control terminal of the switch. The controller is configured to: turn on the switch responsive to a first supply voltage level at the input of the supply circuit; and turn off the switch responsive to a second supply voltage level at the input of the supply circuit.

Auxiliary supply circuit

An example apparatus includes: a pullup circuit coupled to a first USB terminal; a first pulldown circuit coupled to the first USB terminal; a second pulldown circuit coupled to a second USB terminal; a third pulldown circuit coupled to a third USB terminal; a fourth pulldown circuit coupled to a fourth USB terminal; a high-speed termination detection circuit including: a current source including a first supply terminal and a second supply terminal, the first supply terminal coupled to the first USB terminal, the second supply terminal coupled to the second USB terminal; a first comparator including a first comparator terminal and a second comparator terminal, the first comparator terminal coupled to the first USB terminal; and a second comparator including a third comparator terminal and a fourth comparator terminal, the third comparator terminal coupled to the second USB terminal; and a controller including a first control terminal and a second control terminal, the first control terminal coupled to the second comparator terminal, the second control terminal coupled to the fourth comparator terminal.

Methods and apparatus to detect L2 entry and reset in universal serial bus repeaters

A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns 'on' the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

Fail-open isolator

Circuits and systems include a parallel resistor-capacitor (RC) network coupled between a pin and ground, and first and second transistors coupled in source follower configuration with a common gate coupling. The source of the first transistor is coupled to the pin. A first switch couples a drain of the first transistor to the common gate coupling during soft-start (SS) and decouples that connection during over current limit (OCL) sensing, and a second switch couples a drain of the second transistor to the common gate coupling during OCL sensing and decouples that connection during SS. A first current source is enabled deliver a constant current to the pin during SS. A second current source is enabled to generate a reference voltage at the source of the second transistor during OCL, which reference voltage is transferred to the pin by the source follower configuration. A comparator controls the switches to transition from SS to OCL sensing. The comparator output signal is based on a comparison of the voltage at the pin to a threshold voltage.

Multifunction pin for soft start and current limit in voltage converters

A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Data and power isolation barrier

A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

Dual role support for a high-speed capable USB repeater

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Device isolator with reduced parasitic capacitance

An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.

Methods and apparatus to reduce variations for on-off keying transmissions

A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

Communication interface buffer with hot-swap protection

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Bengaluru, India

Anant Shankar Kamath