Intel Corporation

Anant S Deval

Robert J Greiner

Edward Allyn Burton

Stephan Jourdan

Stephen H Gunther

Michael Cornaby

Douglas Robert Huard

Jeremy J Shrall

Amit Kumar Jain

Sergio Carlo Rodriguez

Benson D Inkley

Doug Huard

Arun R Ramadorai

Martin M Chang

Sanjeev S Jahagirdar

Fabrice Paillet

Gerhard Schrom

Srikanth T Srinivasan

Lily Pao Looi

David Lawrence Hill

Tim Frodsham

Jonathan P Douglas

Chee Lim Nge

Derek T Bachand

Michael Zelikson

Alexander Lyakhov

Sin Sim Tan

Selim Bilgin

George Matthew

Nimrod Angel

R Kenneth Hose

Mark R Waggoner

Hong Yun Tan

Rachid Rayess

Ray Ramadorai

Mike Cornaby

Mauricio Aguilar Salas

Pushkar Dixit

Shuan M Conrad

Dave Perchlik

Stephan J Jourdan

Techniques and mechanisms for determining an operational mode of a voltage regulator. In an embodiment, an integrated circuit (IC) die is coupled to receive power from a voltage regulator (VR) via a power delivery network (PDN) which comprises circuitry in or on a substrate, such as that of a printed circuit board. The IC die receives from the substrate information indicating a characteristic of a parasitic impedance at the substrate. Based on the information, a controller unit at the IC die selects one of multiple VR modes which each correspond to a respective one of different parasitic impedance characteristics. The controller then signals the VR to provide the selected mode. In an embodiment one of the VR modes corresponds to a relatively high impedance, and also corresponds to a relatively stable sensitivity function in a frequency range above a control bandwidth.

Device, method and system to determine a mode of voltage regulation based on parasitics of a power delivery network

Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Apparatus and method for proactive power management to avoid unintentional processor shutdown

Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Independent power control of processing cores

An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a mid-point of the at least two switches and an output terminal; a first circuitry to compare a current through the inductor with a threshold current, and to control one or both of the at least two switches, based at least in part on the comparison; and a second circuitry to randomly vary the threshold current over consecutive cycles of switching of the at least two switches.

Reducing electromagnetic interference in switching regulators

Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.

Threshold voltage dependent power-gate driver

In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.

Independent control of processor core retention states

Methods and apparatus to improve integrated circuit (IC) performance across a range of operating conditions and/or physical constraints are described. In one embodiment, an operating parameter of one or more of processor cores may be adjusted in response to a change in the activity level of processor cores (e.g., the number of active processor cores) and/or a comparison of one or more operating conditions and one or more corresponding threshold values. Other embodiments are also described.

Integrated circuit performance improvement across a range of operating conditions and physical constraints

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Portland, OR, United States of America

Anant S Deval