Cree Gmbh

Medical University of South Carolina

Auburn University

Wolfspeed, Inc.

Cree Research Inc.

Anant Kumar Agarwal

Sei-Hyung Ryu

John Williams Palmour

Qingchun Zhang

Lin Cheng

Vipindas Pala

Jason Patrick Henning

Daniel Jenner Lichtenwalner

Scott Thomas Allen

Charlotte Jonas

Sarit Dhar

Mrinal Kanti Das

Edward Robert Van Brunt

Ranbir Singh

Joseph John Sumakeris

Hudson McDonald Hobgood

Jason Ronald Jenny

Michael O'Loughlin

Doyle Craig Capell

Allen Hefner

Sumithra Krishnaswami

Matthew Donofrio

Alexander Viktorovich Bolotnikov

Tangali S Sudarshan

Albert Augustus Burk, Jr

Jason Gurganus

Craig Capell

Dave Grider

Alexander V Suvorov

Sarah Kay Haney

Lori A Lipkin

Allan Ward

John Robert Williams

James Theodore Richmond

D Craig Capell

Edward Harold Hurt

Albert Burk

Erik Maki

Vipindis Pala

James T Richmond, Jr

Matt Donofrio

Sei-Hyung Rya

A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.

Vertical power transistor device

A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm.

Power module for supporting high current densities

A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.

Seminconductor device with spreading layer

Monolithically integrated vertical power transistor and bypass diode

A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.

Field effect transistor devices with buried well protection regions

A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.

Using a carbon vacancy reduction material to increase average carrier lifetime in a silicon carbide semiconductor device

Power module having a switch module for supporting high current densities

Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions

The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

Schottky diode

The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

Bipolar junction transistor structure for reduced current crowding

Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein.

Double guard ring edge termination for silicon carbide devices

Growing community of inventors

Chapel Hill, NC, United States of America

Anant Kumar Agarwal