Tilera Corporation

Massachusetts Institute of Technology

Mellanox Technologies, Ltd.

Incert Software Corporation

Symantec Operating Corporation

Veritas Operating Corporation

Virtual Machine Works, Inc.

Ikos Systems, Inc.

Edx Inc.

Anant Agarwal

David M Wentzlaff

Matthew Mattina

Richard Schooler

Ian Rudolf Bratt

Walter Lee

Patrick Robert Griffin

Robert A Gottlieb

Andrew E Ayers

Vineet Soni

Carl Ramey

Kenneth M Steele

Chyi-Chang Miao

Charles W Selvidge

Bruce Edwards

Christopher D Metcalf

Jonathan William Babb

Matthew L Dahl

Mathew Hostetter

Michelle Leger

Johnathan Babb

Russell Tessier

Mark B Rosenbluth

Christopher J Jackson

Rodric Rabbah

Liewei Bao

Shane Bell

John A Amann

Richard Conlin

Ben Harrison

Kevin Joyce

Christine Deignan

Shripad Nagarkar

Steven D Pudar

An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch. Also disclosed is a direct memory access (DMA) scheme in which sizes of DMA transfers are limited according to whether a cache miss has occurred.

Architecture and programming in a parallel processing environment with a tiled processor having a direct memory access controller

A processor includes a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is associated with information indicating whether data stored in the cache memory is shared among multiple processor cores.

Cache coherency in multiprocessor system

An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.

Transferring data in a parallel processing environment

An interaction environment for presentation of content to a population of users includes either or both of a plurality of cohort interaction environments and one or more content-linked interaction environments.

Online distributed interaction

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Computing in parallel processing environments

A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

Caching in multicore and multiprocessor architectures

An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.

Architecture emulation in a parallel processing environment

Programming in a multiprocessor environment includes accepting a program specification that defines a plurality of processing modules and one or more channels for sending data between ports of the modules, mapping each of the processing modules to run on a set of one or more processing engines of a network of interconnected processing engines, and for at least some of the channels, assigning one or more elements of one or more processing engines in the network to the channel for sending data between respective processing modules.

Programming in a multiprocessor environment

An apparatus comprises a plurality of processor cores, each comprising a computation unit and a memory. The apparatus further comprises an interconnection network to transmit data among the processor cores. At least some of the memories are configured as a cache for memory external to the processor cores, and at least some of the processor cores are configured to transmit a message over the interconnection network to access a cache of another processor core.

Managing cache memory in a parallel processing environment

A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; for each of a first subset of branches in the control flow graph, scheduling a value of an associated branch condition to be broadcast to multiple computation units; for each of a second subset of branches in the control flow graph, representing each instruction dependent on an associated branch condition as a predicated instruction that includes a predicate for computing the associated branch condition; assigning each subset of instructions to one of the computation units for execution on the assigned computation unit; and converting at least some of the predicated instructions in a subset of instructions assigned to a given computation unit into unpredicated instructions that depend on a branch local to the given computation unit.

Compiling code for parallel processing architectures based on control flow

Growing community of inventors

Weston, MA, United States of America

Anant Agarwal