Texas Instruments Corporation

Anand T Krishnan

Srikanth Krishnan

Vijay Kumar Reddy

Cathy A Chancellor

James D Gallia

Haowen Bu

Rajesh B Khamankar

John Anthony Rodriguez

Husam N Alshareef

Malcolm John Bevan

Srinivasan Chakravarthi

Ajith Varghese

Michael Allen Ball

Paul Edward Nicollian

Jayesh C Raval

Juan A Rosal

A method for evaluating gate dielectrics () includes providing a test structure (). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing () is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed () including electrically stressing for a time (t). Following the stressing, post-stress I-V testing is performed () wherein the first, second and third measurements are repeated to obtain post-stress I-V test data. The gate dielectric is evaluated () from the pre-stress and post-stress I-V test data.

Current-voltage-based method for evaluating thin dielectrics based on interface traps

A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

Thermal treatment of nitrided oxide to improve negative bias thermal instability

According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

Method and system for reducing charge damage in silicon-on-insulator technology

A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (V) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.

Method to identify or screen VMIN drift on memory cells during burn-in or operation

Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

System and method for accurate negative bias temperature instability characterization

The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.

Interface improvement by stress application during oxide growth through use of backside films

An embodiment of the invention is an integrated circuithaving antenna proximity linescoupled to the semiconductor substrate. Another embodiment of the invention is a method of manufacturing an integrated circuithaving antenna proximity linescoupled to the semiconductor substrate

Method of manufacturing antenna proximity lines

Integrated circuit having antenna proximity lines coupled to the semiconductor substrate contacts

A semiconductor device ( ) that includes a semiconductor substrate ( ), semiconductor features ( ) located thereover and an insulating photoconductive layer ( ) coupling the semiconductor features ( ). The photoconductive layer ( ) is configured to provide conductivity between the semiconductor features ( ) in a presence of a plasma.

Photoconductive thin film for reduction of plasma damage

One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating substantially prevents processes used to form a second gate dielectric from affecting a first gate dielectric. In an exemplary process, an oxide gate dielectric is grown for peripheral region transistors, a protective coating of silicon nitride is deposited over the peripheral region gate oxide, the oxide and protective coating are etched from a core region, and then a second oxide dielectric is grown for core region transistors while the silicon nitride coating substantially prevents further oxide growth in the peripheral region. The protective coating can also prevent nitridation of the core region gate dielectric from affecting the peripheral region gate dielectric.

Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process

Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric capacitor formed therein is exposed to a processing operation. After processing, the ferroelectric capacitor is measured to determine the extent to which the processing operation polarized the ferroelectric capacitor, and a process related charging value is determined according to the ferroelectric capacitor polarization.

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Farmers Branch, TX, United States of America

Anand T Krishnan