Texas Instruments Corporation

Anand Subramanian

Anand Kannan

Subramanian Jagdish Narayan

Sovan Ghosh

Amal Kumar Kundu

Laxmi Vivek Tripurari

Abhijit Anant Patki

Sunil Rafeeque

Pedro Ramon Gelabert

Ramamurthy Vishweshwara

Uttam Kumar Agarwal

Tanmay Halder

Diljith Mathal Thodi

Venakatesh Guduri

A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

Dynamic biasing circuit

A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Programmable gain amplifier with programmable resistance

A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.

Sampled moving average notch filter for ripple reduction in chopper stabilized operational amplifiers

A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

Analog-to-digital converter with dynamic range enhancer

A system includes: a reference buffer coupled to an input supply voltage; an analog-to-digital converter (ADC) coupled to an output of the reference buffer; and an output capacitor coupled between the output of the reference buffer and a ground node. The reference buffer includes: an integrator; an internal capacitor coupled between an output of the integrator and the ground node; a first gain stage with an input coupled to the output of the reference buffer; and a second gain stage with an input coupled to the output of the integrator. The output of the first gain stage is combined with the output of the integrator using a combine circuit.

Reference buffer with integration path, on-chip capacitor, and gain stage separate from the integration path

The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a transition node. A slope of the transition signal is greater than a slope of the supply voltage. A first diode connected transistor receives the supply voltage. A first capacitor is coupled to the first diode connected transistor. An inverter is coupled to the first diode connected transistor and generates an enable signal when the supply voltage is below a threshold voltage.

Method and apparatus for a brown out detector

A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.

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Bengaluru, India

Anand Subramanian