Nvidia Corporation

Anand Srinivasan

Brad W Simeral

David G Reed

Dmitry Vyshetsky

Joshua Titus

Roman Surgutchik

Robert William Chapman

Hari Unni Krishnan

Roman Surgutchick

Brian K Langendorf

Sean Jeffrey Treichler

Edward M Veeser

James P Reilley

A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.

Data path controller with integrated power management to manage power consumption of a computing device and its components

A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.

Apparatus, system, and method for a fast data return memory controller

A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.

Apparatus, system, and method for fast read request transfer through clock domains

A bus interface unit is adapted to receive transaction requests for at least two different targets. The bus interface unit monitors a capacity of a resource associated with servicing transaction requests to the targets, such as a posted write buffer. If a transaction request would fill the resource beyond a current remaining capacity of the resource such that the execution of other pipelined transactions would become stalled, the bus interface generates a retry response so that the request is retried at a later time, permitting other transactions to proceed while the resource drains.

Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface

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San Jose, CA, United States of America

Anand Srinivasan