Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Anand Pande

Darren Duane Neuman

Ramanujan K Valmiki

Brian Francis Schoner

Kenneth R Kindsfater

Sathish Kumar

Lakshmanan Ramakrishnan

Lionel D'Luna

Syed Mohammed Ali

K Naresh Chandra Srinivas

Naresh Chandra Srinivas Koppineedi

Praveen Vadakkumthodam Radhakrishnan

Ravindra Bindus

A system and method for processing graphics are provided. Pixel data may be received for a pixel block. Endpoints for the values of the pixels in the pixel block may be determined. A weight for the pixels in the pixel block may be determined in four dimensions corresponding to the endpoints. A compressed data block representative of the pixel block may be generated in response to the endpoints for the pixel block and the weight for the pixels of the pixel block in the four dimensions corresponding to the endpoints.

System and method for graphics compression

A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.

Method and system for processing video data in a multipixel memory to memory compositor

Flesh-tones corrections may be performed to correct color shifts that may occur in transmitted video frames wherein chroma information corresponding to flesh-tone video pixels may be distorted. A target region may be determined based on a determined flesh-tones region within a spatial representation of chroma in video color space, such as Y'CrCb. The flesh-tones correction may utilize one or more methodologies based on an elliptical shape and/or a triangular shape algorithm(s). A video processing system may be utilized to analyze chroma information of received video pixels and/or to perform flesh-tones corrections by shifting the chroma value of received video pixels towards good flesh-tones regions to compensate for possible distortions. The video processing system may perform conversion calculation and/or shift operations dynamically. The video processing system may also utilize lookup tables (LUTs) to convert received chroma values. The LUTs may be programmable to enable modifying and/or updating of the system.

Method and system for automatic correction of flesh-tones (skin-tones)

Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

System for designing data structures

Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

Dual numerically controlled delay logic for DQS gating

Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Schmoo runtime reduction and dynamic calibration based on a DLL lock value

A system and method for scan testing an NCDL and latches controlled by the NCDL is presented. The NCDL is controlled by control logic, a switch is used to control the latches by a clock signal that is not controlled by the control logic. A controllability circuit provides test vectors to, and controls, the NCDL. The outputs of the NCDL are observed by an observability circuit that captures the outputs of the NCDL.

Growing community of inventors

Bengaluru, India

Anand Pande