Amazon Technologies, Inc.

Anand Narayan Acharya

Bijendra Singh

Kenneth Wayne Patton

Himabindu Sajja

Kari Ann O'Brien

Sravya Kusam

A packet processor or packet processing pipeline may implement programmatic selection of load balancing output for forwarding paths. Programmatic selection for load balancing among forwarding paths may be enabled or disabled at one or more stages. If programmatic selection is enabled when network packets are received, a programmatically identified path may be provided as the selected path of a load balancing scheme at a stage. Forwarding of the packet may then be performed according to the selected path.

Programmatic selection of load balancing output amongst forwarding paths

Systems, methods, apparatus and computer readable medium is disclosed for extending the Virtual Routing and Forwarding (VRF) in the network using embedded source identifiers in the packets. An example apparatus may include ports, memory and processing logic. The memory may include VRF routing tables corresponding to respective VRF domains and a list of media access control (MAC) addresses, wherein each MAC address in the list is linked to one of the respective VRF routing tables. The processing logic may be configured to receive an ingress packet at a port, identify a matching MAC address in the list that matches a source identifier of the ingress packet, and process the ingress packet according to the respective VRF domain associated with the matching MAC address that matches the source identifier.

Extending virtual routing and forwarding using source identifiers

Systems, methods, apparatus and computer readable medium are disclosed for extending Virtual Routing and Forwarding (VRF) for a network. An example apparatus includes ports, memory and processing logic. The memory includes VRF routing tables corresponding to respective VRF domains. The memory may also include a list of media access control (MAC) addresses, wherein each MAC address in the list is linked to one of the respective VRF domains. The processing logic may be coupled to access the memory and coupled to the ports. The processing logic may be configured to receive an ingress packet at a port of the apparatus, identify a VRF domain that the ingress packet belongs to, process the ingress packet according to the VRF domain, and optionally generate an egress packet, by embedding/writing a MAC address in the egress packet that acts as a source identifier for the respective VRF domain.

Growing community of inventors

Austin, TX, United States of America

Anand Narayan Acharya