Qualcomm Incorporated

Anand Meruva

Jeffrey Mark Hinrichs

Dinesh Jagannath Alladi

Lei Sun

Seyed Arash Mirhaj

Yuhua Guo

Yongjian Tang

Yong Xu

Elias Dagher

Boris Andreev

Chieh-Yu Hsieh

Masoud Ensafdaran

Balasubramanian Sivakumar

Prince Mathew

Vikas Mahendiyan

Yuxin Li

A delay buffer includes a delay device having an input, an output, and a current terminal. The delay buffer also includes a current circuit coupled between a rail and the current terminal. The current circuit includes transistors and switches. Each one of the switches is coupled in series with a respective one of the transistors between the rail and the current terminal.

Compact digital delay locked loop

A phase interpolator includes a sampling circuit configured to capture samples of an output of the phase interpolator, a delay circuit configured to delay sampling by the sampling circuit, a comparator configured to provide a comparison signal that indicates whether voltage of the samples exceed a reference voltage, and a counter responsive to the comparison signal and configured to provide an output that controls an operating point of the phase interpolator. The phase interpolator my further include a pair of driver circuits configured to concurrently drive the output of the phase interpolator.

Wide frequency phase interpolator

A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

DDR phy parallel clock paths architecture

Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.

Flash-successive approximation register (SAR) hybrid analog-to-digital converter (ADC)

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

Calibration for time-interleaved analog-to-digital converters and signal generators therefor

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San Diego, CA, United States of America

Anand Meruva