Synopsys, Inc.

Anand Kumar Rajaram

Tao Lin

Aiqun Cao

Min Pan

Jieyi Long

Michael Bezman

Feng Sheng

An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

Clock network power estimation for logical designs

Systems and techniques are described for context aware clock tree synthesis (CTS). A probability value can be computed for each clock sink in the set of clock sinks, wherein each probability value represents a probability that the corresponding clock sink has a critical clock latency. Next, the set of clock sinks can be clustered into a set of clock sink clusters based on the probability values. An optimization goal for each clock sink cluster can be selected, and an optimized subtree can be constructed for each clock sink cluster based on the selected optimization goal. The synthesized clock tree can be obtained by combining the optimized subtrees.

Clock tree synthesis based on computing critical clock latency probabilities

A global optimization method to synthesize and balance the clock systems in a multimode, multi-corner, and multi-domain design environment is described. The method builds a graph representation for a clock network. The method determines an optimal clock network balancing solution for the clock network by applying linear programming to the graph. To apply linear programming to the graph, the method generates a set of constraints for the graph and determines a proper insertion delay for each edge of the graph by solving for a minimal skew based on the set of constraints. The method implements the optimal clock network balancing solution.

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Austin, TX, United States of America

Anand Kumar Rajaram