Intel Corporation

Anand K Enamandram

Krishnakanth Venkata Sistla

Ramamurthy Krithivas

Eswaramoorthi Nallusamy

Robert A Branch

Efraim Rotem

Mahesh S Natu

Nir Rosenzweig

Jorge Pedro Rodriguez

Dorit Shapira

Kerry Vander Kamp

Daniel Cartagena

Siddhartha Chhabra

Hormuzd M Khosravi

Wei P Chen

David I Poisner

Yen-Cheng Liu

Malay Trivedi

Sivakumar Radhakrishnan

Yuri I Krimon

Amit Kumar Srivastava

Vinit Mathew Abraham

Tina C Zhong

Russell J Wunderlich

Handeep Kaur

Tiffany J Kasanicky

Majid Shushtarian

Manjula Peddireddy

Jayasekhar Tholiyil

Michael J Karas

Jeffrey A Pihlman

James Goffena

Christine Watnik

Jared W Havican

Monam Agarwal

Vishal Mannapur

Jason Voelz

Cheng-Wein Lin

Irene Johansen

Wei Chen

Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.

Flexible provisioning of coherent memory address decoders in hardware

Methods and apparatus to reduce register access latency in split-die SoC designs. The method is implemented on a platform including a legacy socket and one or more non-legacy (NL) sockets comprising split-die System-on-Chips (SoC)s including multiple dielets interconnected with a plurality of Embedded Multi-Die Interconnect Bridges (EMIBs). The dielets include core dielets having cores, cache controllers and memory controllers. The method provides an affinity between a control and status registers (CSRs) memory range for the NL sockets such that CSRs in the memory controllers for multiple core dielets are programmed using transactions forwarded along core-to-cache controller datapaths that avoid crossing EMIBs. In one aspect, a transient map of address ranges is created that includes a respective Sub-NUMA Cluster (SNC) range allocated for the NL sockets, with a range of CSR addresses for accessing CSRs in the memory controllers for the NL sockets being stored in the respective SNC ranges.

Method to reduce register access latency in split-die SoC designs

A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks and determine whether the actual topology matches the desired topology as described in the cluster remapping table.

Cluster identifier remapping for asymmetric topologies

An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Power management based on real time platform power sensing

Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Circuitry and methods for spatially unique and location independent persistent memory encryption

Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH. The multi-socket platforms include a platform with a bootable CPU coupled to one or more non-legacy CPUs and employing multiple IO-expanders and platform with a legacy CPU coupled to one or more non-legacy CPUs and coupled to a legacy PCH, and further including one or more PCHs coupled to the non-legacy CPU(s) implemented as IO-expanders.

Platform controller hub (PCH) chipsets in platforms as extended IO expander(s)

Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Accessing a memory using index offset information

Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

Techniques to collect crash data for a computing system

Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.

Technology to ensure sufficient memory type range registers to fully cache complex memory configurations

Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

Micro-architectural techniques to minimize companion die firmware loading times in a server platform

Apparatuses, methods and storage medium associated with characterizing a fluid sample based on response of a non-planar structure are disclosed herein. In embodiments, an apparatus may include a non-planar structure having an exterior (e.g., a curved exterior) and a core having a content to change (e.g., by osmosis) responsive to application of the fluid sample to the non-planar structure. The apparatus may include one or more processors, devices, and/or circuitry to identify a value indicative of a characteristic of the fluid based on the measurement. Other embodiments may be disclosed or claimed.

Characterizing a fluid sample based on response of a non-planar structure

Growing community of inventors

Folsom, CA, United States of America

Anand K Enamandram