Avago Technologies International Sales Pte. Limited

Broadcom Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Anand Jitendra Vasani

Jun Cao

Afshin Momtaz

Ali Nazemi

Adesh Garg

Burak Catli

Arvindh Iyer

Jiawen Zhang

Jan Mulder

Namik Kocaman

Tamer Mohammed Ali

Jan Roelof Westra

Ullas Singh

Meisam Honarvar Nazari

Henry Arnold Park

Ramy Awad

Seong-Ho Lee

Kun Chuai

Hyo Gyuem Rhew

Alireza Nilchi

Hyung-Joon Jeon

Lakshmi Rao

Mohammed Abdul-Latif

Amr Amin Hafez Amin Abou-El-Sonoun

Seong Ho Lee

A circuit for driving digital-to-analog converter (DAC) comprising a serializer configured to combine multiple signals to one input signal to drive a forward inverter coupled to a first node with a first impedance in serial configuration and a first capacitance in shunt configuration. The circuit includes a chain of inverters coupled in series to transfer the input signal from the first node to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter between the third node and the first node to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node. A second feedback inverter can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

DFE-based peaking techniques for high-speed transmitters

In some implementations, the device may include a first circuit receiving an input signal having a first frequency, the first circuit including a first node and a second node. The device may include a second circuit receiving an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node, a first inductor coupled between the first node of the first circuit and the first node of the second circuit. The device may include a second inductor coupled between the second node of the first circuit and the second node of the second circuit, a first switch coupled between the first node of the second circuit and the second node of the second circuit, at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state.

Wide frequency range high speed clock multiplexer

Disclosed herein are related to systems and methods for providing different power supply levels. In one aspect, a first circuit generates a first signal having a first amplitude according to a first supply voltage. A latch may be coupled to a resistor of a plurality of resistors coupled in series. One end of the resistor may be configured to provide to the latch a second supply voltage higher than the first supply voltage according to a third supply voltage higher than the second supply voltage, and another end of the resistor may be configured to receive the third supply voltage. The latch may modify the first signal to provide a second signal, according to the second supply voltage. An amplifier may amplify the second signal to provide a third signal having a second amplitude larger than the first amplitude, according to the third supply voltage.

Power supply generation for transmitter

Systems and methods for data multiplexing include or use a data serializer having a first set of four serializer outputs and a second set of four serializer outputs. The systems and methods also use or include a pair of 4 to 1 multiplexers each having four first multiplexer inputs and one first multiplexer outputs and a 2 to 1 multiplexer having two multiplexer inputs and one multiplexer output.

High-speed transmitter including a multiplexer using multi-phase clocks

A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.

Pre-driver peaking technique for high-speed DACs

A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Multi-segmented all logic DAC

A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

High-speed, low-power reconfigurable voltage-mode DAC-driver

A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Low-power high swing CML driver with independent common-mode and swing control

Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

Low latency high bandwidth CDR architecture

A multi-mode driver and method therefore includes a plurality of amplifiers, an adjustable load block, and adjustable current supply circuitry that selectively adjusts current magnitudes supplied to at least one of the plurality of amplifiers. The multi-mode driver can operate in a KR mode with a higher voltage supply, an SR4 mode with the higher voltage supply, and an SFI mode with a lower voltage supply. To support these modes, the multi-mode driver selectively operates a plurality of amplifiers, adjusts current magnitudes supplied to the amplifiers, and selectively adjusts an adjustable load. Thus, the multi-mode driver is operable to selectively and efficiently produce high swing and low swing output signals and to efficiently operate with any one of a plurality of supplies. The driver includes selectable loads and parallel-coupled amplifier devices that are selected based on mode.

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Irvine, CA, United States of America

Anand Jitendra Vasani