Texas Instruments Corporation

Anand J Reddy

Ju-Ai Ruan

Howard L Tigelaar

Richard L Guldi

Tae S Kim

Changming Jin

Phillip D Matz

Sameer Kumar Ajmera

Sopa Chevacharoenkul

Basab Chatterjee

Kenneth Joseph Newton

Ching-Te Lin

One aspect of the invention provides a method of forming a semiconductor device (). One aspect includes forming transistors () on a semiconductor substrate (), forming a first interlevel dielectric layer () over the transistors (), and forming metal interconnects () within the first interlevel dielectric layer (). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer () over the metal interconnects () and the first interlevel dielectric layer () within a deposition tool. An adhesion layer () is formed on the SiCN layer (), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer () is formed over the adhesion layer ().

Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer

A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Reduction of punch-thru defects in damascene processing

A subset test module and associated methodology for utilizing the same are disclosed that facilitate identification of process drift in semiconductor fabrication processing. A test wafer having a plurality of die formed thereon has a plurality of test modules formed within the die. The plurality of test modules are substantially the same from die to die, and the respective modules similarly include a plurality of test structures that are substantially the same from module to module. Corresponding test structures within respective modules on different die are inspected and compared to one another to find structures that are sensitive to process drift. One or more structures that experience differences from module to module on different die are utilized to develop one or more test modules that can be selectively located within production wafers and monitored to determine whether process drift and/or one or more other aberrant processing conditions are occurring.

Sensitive test structure for assessing pattern anomalies

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Palo Alto, CA, United States of America

Anand J Reddy