Texas Instruments Corporation

Anand Hariraj Udupa

Sandeep Kesrimal Oswal

Jagannathan Venkataraman

Visvesvaraya Appala Pentakota

Nitin Kumar Agarwal

Hussam Ahmed

Hari Babu Tippana

Aravind Miriyala

Raja Reddy Patukuri

Shakti Shankar Rath

Vikas Kumar Sinha

Aatish Chandak

Prabin Krishna Yadav

Eeshan Miglani

Neeraj Shrivastava

Vineet Mishra

Gautam Salil Nandi

Ravishankar S Ayyagari

Supriyo Palit

Suhas R Kulhalli

Visvesvaraya Pentakota Appala

Kiran Rajmohan

Pradeep G Nair

Sindhuja Sridharan

Midhun Raveendran

Visvesvararaya A Pentakota

H Mohammed Shuaeb Fazeel

Hussam Ahmed P

Antoine Lourdes Praveen Aroul

Anand Reghunathan

An example apparatus includes: calibration circuitry configured to determine a second current at a second terminal of a second impedance circuit based on a first parasitic capacitance, a first impedance value, a third impedance value, a first voltage, and a second voltage; determine a third voltage at a second terminal of a second impedance circuit based on the first parasitic capacitance, a second impedance value, the third impedance value, the second voltage, and the second current; and determine a second parasitic capacitance between the second terminal of the second impedance circuit and the second terminal of a fifth impedance circuit based on the second current, the third voltage, a third current at the second terminal of the fifth impedance circuit, and a fourth voltage at the second terminal of the fifth impedance circuit.

Methods and apparatus for determining parasitic capacitances

An ECG signal acquisition system includes a first amplifier which has a non-inverting input adapted to be coupled to a first differential input, an inverting input adapted to be coupled to a second differential input, and an output. The system includes first and second biasing resistors coupled between the non-inverting and inverting inputs of the first amplifier. The system includes an average estimation circuit which has a first input coupled to the non-inverting input of the first amplifier and a second input coupled to the inverting input of the first amplifier. The system includes a driver amplifier which has an inverting input coupled to the output of the average estimation circuit, a non-inverting input coupled to receive a reference common-mode voltage, and an output. The system includes a low-pass filter coupled between the output of the driver amplifier and the biasing resistors.

AC-coupled electrocardiogram signal acquisition system with enhanced common mode rejection

A system may comprise: an excitation current source; a first electrode coupled to the excitation current source; and a second electrode coupled to the excitation current source. The first and second electrodes may be configured to pass an excitation current from the excitation current source through a human body. First and second calibration resistors may be coupled to and positioned between the excitation current source and the first electrode. Third and fourth calibration resistors may be coupled to and positioned between the excitation current source and the second electrode. The system may also comprise a sensor configured to measure voltages across each of the first, second, third, and fourth calibration resistors.

Calibrating body impedance measurement systems

A bio-sensing device (and method) calibrates a time period used to make bio-physical measurements. The device initiates a light source sense phase followed by a first ambient sense phase and a second ambient sense phase. In the light source sense phase, the device is configured to receive a digital value indicative of current through a photodetector while the light source circuit is enabled and in each of the first and second ambient sense phases, the device is configured to receive digital values while the light source circuit is disabled. The device iteratively varies the time period between the phases until the digital value received during the first ambient sense phase is within a threshold of the digital value received during the second ambient sense phase. It then applies the same time separation between the light source sense phase and the ambient phase thereby equalizing the magnitude of the ambient light in the two phases.

Bio-sensing device with ambient light cancellation

At least some embodiments are directed to a light detection system comprising a photodiode, a transimpedance amplifier (TIA) having a differential output and a differential input coupled across the photodiode, a first bias current source coupled to an anode of the photodiode, and a second bias current source coupled to a cathode of the photodiode. The system also comprises a dynamic control logic coupled to the first and second bias current sources and configured to vary bias currents provided by the first and second bias current sources based on the differential output such that the photodiode is reverse-biased.

Bias currents to reverse-bias photodiode in light detection system

The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.

Measuring electrode impedance in an impedance measurement circuit

The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source that generates an excitation signal. A switched resistor network is coupled to the excitation source, and generates an output signal in response to the excitation signal. A sense circuit is coupled to the switched resistor network, and generates a sense signal in response to the output signal. A comparator is coupled to the sense circuit, and generates a clock signal in response to the sense signal. A mixer is coupled to the sense circuit, and multiplies the sense signal and the clock signal to generate a rectified signal. A low pass filter is coupled to the mixer and filters the rectified signal to generate an averaged signal. A processor is coupled to the low pass filter and measures a body impedance from the averaged signal.

Impedance measurement circuit

DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.

DC offset correction with low frequency signal support circuits and methods

A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.

Voltage reference with improved linearity addressing variable impedance characteristics at output node

Increasing the input common-mode range of a circuit which accepts differential signals as inputs. Such an increase may be attained by correcting an input signal at continuous levels or at 2 or more discrete levels) without changing the strength represented by the input signal. In an embodiment, the common-mode component of an input signal is measured, and a correction voltage proportional to the difference between the measured common-mode component and a reference voltage, is generated. The correction voltage is coupled to the input terminals of the differential circuit to correct for any deviations from a desired level of common-mode voltage at the input terminals of the differential circuit. The approaches are applied to a switched-capacitor differential amplifier used in a sample-and-hold portion of an ADC.

Increasing the common mode range of a circuit

With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.

Analog to digital converter with improved input overload recovery

A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)

Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Enhancing SNR and throughput performance of integrated circuits

The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.

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Bengaluru, India

Anand Hariraj Udupa