International Business Machines Corporation

Globalfoundries Inc.

Lenovo (singapore) Pte. Ltd.

Anand Haridass

Roger Donell Weekly

Daniel Mark Dreps

Prasanna Jayaraman

Andreas Huber

Sungjun Chun

Frank David Ferraiolo

Arun Joseph

Bao G Truong

Daniel Douriet

Colm Brian O'Reilly

Edgar Rolando Cordero

Diyanesh B Chinnakkonda Vidyapoornachary

Michael Jay Shapiro

Louis Bennie Capps, Jr

Ronald Edward Newhart

Wiren Dale Becker

Joel David Ziegelbein

Robert J Reese

Erich Klink

Robert Walter Berry, Jr

Bao Gia-Harvey Truong

Saravanan Sethuraman

Charles Robert Lefurgy

Diwesh Pandey

Jean Audet

Tony Emile Sawan

Glenn Graham Daves

Rahul Rao

Pradeep Kumar Nalla

Diyanesh B Vidyapoornachary

Robert Brett Tremaine

David John Krolak

Jinwoo Choi

Gerard M Salem

Jochen Supper

John Cummings Schiff

Diyanesh B C Vidyapoornachary

Jesus Montanez

Spandana V Rachamalla

Sreekala Anandavally

Xiaomin Shen

Joanne Ferris

Subramanian Srikanteswara Iyer

Michael Richard Ouellette

Michael Fan Wang

Tingdong Zhou

Girisankar Paulraj

Thomas Strach

Joachim Gerhard Clabes

Jason Lee Frankel

James Douglas Jordan

Nagashyamala R Dhanwada

Venkata K Tavva

Warren D Dyckman

Anshuman Khandual

Vidhya Shankar Venkatesan

Joseph James Cahill

Dierk Kaller

Shashidhar Reddy

Shiladitya Ghosh

Brian Leslie Singletary

Subrat K Panda

Ming Yin

Robert W Berry

Gisbert Gerhard Thomke

Diyanesh Babu Chinnakkonda Vidyapoornachary

Dulce M Altabella Cabrera

A method stores data that handles page faults in an appropriate memory device based on a standing memory policy. One or more processors receive user requested memory buffer attributes that describe memory buffer attributes needed for various processes. The processor(s) store the user requested memory buffer attributes in an operating system virtual memory representation that describes various types of memories used by the system, create a standing memory policy based on the user requested memory buffer attributes, and store data on an appropriate memory device based on the standing memory policy. The processor(s) receive a page fault, which is based on the data being called by a process but not being currently mapped by a memory management unit (MMU) into a virtual address space of the process. The processor(s) then retrieve and return the data stored on the appropriate memory device in order to address the page fault.

Mapping memory allocation requests using various memory attributes

Embodiments relate to monitoring computing hardware in a computing infrastructure facility. Image data and environmental data are received and a current operational status for a computing hardware component is determined from the image data. A hardware operational status tracking model and environment tracking model for the computing hardware component are updated. Embodiments can perform a root cause analysis if the current operational status is a fault status to determine if the fault status was caused by environmental conditions.

System to monitor computing hardware in a computing infrastructure facility

A method, computer system, and computer program product for human relationship-aware augmented display are provided. The embodiment may include identifying one or more potential viewers utilizing real-time sensor data. The embodiment may also include extracting relationship information related to relationships among each identified viewer and one or more companions based on a plurality of data from a plurality of databases. The embodiment may further include creating a relationship graph based on the extracted relationship information. The embodiment may also include determining a relationship model based on the created relationship graph. The embodiment may further include mapping the determined relationship model to content. The embodiment may also include augmenting display systems with the content. The embodiment may further include displaying the augmented content on one or more display systems.

Human relationship-aware augmented display

An approach for recommending an activity during travel. The approach includes receiving a request for a travel destination and a desired arrival time. Furthermore, the approach determines a route to the travel destination and retrieves external data based on the route. Based on the retrieved data and the route, the approach calculates and outputs an initial activity list. And the approach measures vehicle dynamics based on one or more motion sensors and updates and outputs the activity list based on the vehicle dynamics.

Activity recommendation based on a real-time mapping between activity characteristics and autonomous vehicle dynamics

Systems, methods, and computer-readable media are disclosed for virtualizing memory compute function resources to improve resource utilization and system performance are disclosed. A virtualized hypervisor may be provided that is configured to instantiate a respective memory function controller of each memory controller present in a system/device. The virtualized hypervisor may be further configured to maintain the memory function controllers and their corresponding memory compute functionality as shareable resources that can be allocated to system components upon request. The virtualized hypervisor may allocate a memory function controller and its corresponding memory compute functionality to a system component, and may further provide the system component with an exclusive grant of memory compute pages that can be utilized by the allocated memory function controller to execute a memory compute function to perform one or more operations (e.g., one or more computations) on behalf of the system component.

Virtualization of memory compute functionality

A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.

Leakage power characterization at high temperatures for an integrated circuit

A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.

Formal verification driven power modeling and design verification

A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-&#xe0;-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-&#xe0;-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.

Detecting cross-talk on processor links

A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition.

According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.

Memory power management and data consolidation

In a method for designating cooling fan control management in a computing system, a processor causes one or more cooling fans to be managed by a first process, wherein the first process utilizes a first set of temperature sensors of a plurality of temperature sensors. A processor receives temperature data from a first set of temperature sensors. A processor determines a second process to manage the one or more cooling fans, based on the received temperature data from the first set of temperature sensors, wherein the second process utilizes a second set of temperature sensors of the plurality of temperature sensors.

Multiple level computer system for temperature management for cooling fan control

A computer-implemented method includes capping the amount of power available to each of a plurality of compute nodes, and managing power allocation among subsystems within each of the compute nodes according to the requirements of workloads assigned to each of the compute nodes. The method further comprises reporting an actual performance level and performance capability for each subsystem within each of the plurality of compute nodes, and monitoring parametric data for a particular workload. A target compute node is identified from among the compute nodes, wherein the target compute node would be capable of performing the particular workload if power was reallocated from a first subsystem to a second subsystem within the target compute node. The particular workload is then assigned to the target compute node. Optionally, assigning the particular workload may include migrating the workload to the target compute node from another of the compute nodes.

Subsystem-level power management in a multi-node virtual machine environment

A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.

System interconnect dynamic scaling handshake using spare bit-lane

Growing community of inventors

Austin, TX, United States of America

Anand Haridass