Megachips Corporation

Anand Gopalan

Wenjing Yin

Shankarram Athreya

Takahiro Itagaki

Sarath Chandrasekhar Venkatesh Kumar

A system for cancelling offset includes a gain circuit. The gain circuit may include a transistor circuit connected to a pair of input nodes and configured to convert an input signal to an output signal so that the output signal has a gain compared with the input signal. The gain circuit also may include a pair of output nodes configured to receive the output signal from the transistor circuit. The gain circuit is configured to cause a voltage change at one of the output nodes relative to another output node, in response to the gain circuit receiving a feedback offset correction signal. This effectively cancels at least a portion of an offset in the output signal.

Offset cancellation with minimum noise impact and gain-bandwidth degradation

A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.

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Anand Gopalan