Texas Instruments Corporation

Qualcomm Incorporated

Anand Devendra Kudari

Karthik Subburaj

Timothy Bryan Merkin

Ranjit Kumar Dash

Lakshmanan Balasubramanian

Michael James Mills

Arvindh Rajasekaran

Vinayakumar Prakash Mallapur

Srikanth Jatavallabhula

Aswin Srinivasa Rao

Prashanth Pai

An apparatus includes an amplifier configured to compare a feedback input, corresponding to a voltage of an output voltage node, with respect to a reference input and to provide a control output to control the output voltage node based on a difference between the feedback input and the reference input. At least two source circuits are coupled with the output voltage node. Each of the source circuits are configured to provide respective voltage sources to supply electrical power to the output voltage node.

Multi-input voltage regulator

Methods, devices, apparatuses, and systems may provide integrated combined current sensing for parallel charging architecture. In one embodiment a charger includes a first charging device that includes a switching circuit having a switching output configured to be coupled to a first terminal of an inductive element. The first charging device further includes a charging terminal configured to couple a second terminal of the inductive element to a battery terminal to provide a first power source to charge a battery coupled to the battery terminal. The first charging device further includes a charge current sense element coupled between the charging terminal and the second terminal of the inductive element. The charge current sense element is configured to sense a charge current at the charging terminal. The circuit further includes a second charging device that includes a second power source coupled to the second terminal such that the charge current comprises current from the first charging device and the second charging device.

Parallel charging architecture

Power supplies combining a switching-mode power supply in parallel with a current source can improve maximum load current capability. The current source can be turned on, or the amount of current supplied by the current source increased, when there is a heavy load current demand, for example, when the load current demand is more than the current rating of the switching-mode power supply. The duty cycle of the output stage of the switching-mode power supply can be used to determine the load current demand. The current source may increase the maximum output current of the power supply beyond the maximum output current of the switching-mode power supply. For example, the current source may add 0.5 A to the current capability of a 2.5 A switching-mode power supply.

Switching-mode power supply with helper current source

Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data '1' or '0' to be transmitted, &#x2018;M&#x2019; or &#x2018;M+1&#x2019; clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

Binary frequency shift keying with data modulated in digital domain and carrier generated from intermediate frequency

A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.

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Karnataka, India

Anand Devendra Kudari