Cohesity, Inc.

Qualcomm Incorporated

Texas Instruments Corporation

Anand Bhat

Harsha Jagannati

Anil Kumar Boggarapu

Nishi Bhushan Singh

Ashutosh Anand

Arvind Jagannath

Rajesh Kumar Tiwari

Abhinav Kothiala

Shankarnarayan Bhat

Aishwarya Dubey

Puneet Sabbarwal

Praveen Raghuraman

Naishad Parikh

Pranjal Tiwari

Nikhil Sudhakaran

Devadatta Bhat

Pradeep Periasamy

Tamilselvi Natarajan

Yatin R Acharya

Sanjay Muchini

Arun Balachandar

A response communication that includes one or more data packets is received at a broker associated with a storage node of a plurality of storage nodes via a virtual network associated with the plurality of storage nodes of a storage system. The one or more data packets are provided, via the virtual network associated with the storage nodes, to a tenant communication component associated with an intended destination. A connection between the broker and the tenant communication component associated with the intended destination is terminated. A new connection between the intended destination and the tenant communication component associated with the intended destination is established. The new connection is associated with a virtual network associated with a storage tenant. The one or more data packets are sent to the intended destination via the virtual network associated with the storage tenant.

Secure communications of storage tenants that share a storage cluster system

One or more data packets at a storage node of a storage cluster system is received via a virtual network associated with a storage tenant. A connection between the storage tenant and a tenant communication component of the storage cluster system is terminated. A new connection is established between the tenant communication component of the storage cluster system and a destination associated with the one or more data packets. The one or more data packets are provided to the destination associated with the one or more data packets using a virtual network associated with storage nodes of the storage cluster system.

A first set of one or more tenant communication components are configured to communicate with a first separate system component of a first storage tenant via a first virtual network. A second set of one or more tenant communication components are configured to communicate with a second separate system component of a second storage tenant via a second virtual network. The second virtual network is separate from the first virtual network. A plurality of tenant communication components of the storage cluster system including the first set of one or more tenant communication components and the second set of one or more tenant communication components are configured to communicate internally in the storage cluster system via a third virtual network separate from the first virtual network and the second virtual network.

At least a portion of a virtual machine is hosted on at least one node of a first subset of a plurality of nodes of a secondary storage system. The virtual machine comprises a plurality of portions that can be distributed between the plurality of nodes and is configured into a first state of a plurality of states, such that, in the first state, the plurality of portions is distributed between a first subset of the plurality of nodes and each of the first subset of nodes stores a portion of the virtual machine in its corresponding storage device. A node from the second subset of the plurality of nodes to host the virtual machine in a second state of the plurality of states is selected based on at least one of storage, memory or processing resources of one or more nodes of a second subset of the plurality of nodes.

Hosting virtual machines on a secondary storage system

A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.

Continuous write and read operations for memories with latencies

A method and apparatus for reducing memory built-in self-test (MBIST) area by optimizing the number of interfaces required for testing a given set of memories is provided. The method begins when memories of a same configuration are grouped together. One memory is then selected from each of the groups. MBIST insertion is then performed for a selected group of memories, and the selected group of memories contains memories of different configurations. Control logic is used to select each group of memories separately. The memory group under test may also be selected using programmable user bits. An apparatus is also provided. The apparatus includes: a controller, at least one memory interface in communication with the controller, at least one control logic cloud in communication with the at least one memory interface; and at least one bit bus.

Method and apparatus for multiple memory shared collar architecture

Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Method and apparatus for optimized memory test status detection and debug

A scannable storage circuit includes a scan enable input, a storage element having a Node coupled to a data output buffer for driving a data output terminal. The data output buffer includes an inverter; a transmission gate having a first MOS transistor and a second MOS transistor with sources and drains coupled to each other, drains coupled to an output of the inverter and sources coupled to the data output terminal and gates coupled to the scan enable input and an inverted scan enable input. A third MOS transistor and a fourth MOS transistor is coupled to the sources of the first and second MOS transistors, the third MOS transistor and fourth MOS transistor are configured to pull up or pull down the data output terminal in response to a first control signal and a second control signal respectively. A scan output is generated from the output of the inverter.

Programmable scannable storage circuit

A system, circuit, and device for asynchronously scan capturing multi-clock domains. A system includes a shift register configured to process select data for selecting a clock domain at a time in response to a scan capture pulse and a one-hot n-to-2decoder connected to the shift register and configured to generate one-hot code based on the select data. The system also includes integrated clock gating cells connected to the one-hot n-to-2decoder, where the scan capture pulse is applied to each one of the integrated clock gating cells, and where only one of the integrated clock gating cells associated with the clock domain is enabled when the one-hot code is processed by the integrated clock gating cells. Further, the system includes multiplexers connected to the integrated clock gating cells, where the multiplexers are configured to forward the scan capture pulse to the clock domain.

Decoded register outputs enabling test clock to selected asynchronous domains

A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automatic test pattern generation (ATPG)). Due to the programmability of delay magnitude, the burden on a designer to achieve synchronization of the data input with the clock signal while testing, is reduced.

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Bengaluru, India

Anand Bhat