Synopsys, Inc.

Anand Arunachalam

Mahesh A Iyer

Jing Chyuarn Lin

Mohammad Ziaullah Khan

Xinwei Zheng

Suman Chatterjee

Xiaoyan Yang

Mustafa Kamal

Dongxiang Wu

Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.

Method and apparatus for automatic relative placement generation for clock trees

Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops.

Placement of single-bit and multi-bit flip-flops

Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.

Method and apparatus for automatic relative placement rule generation

Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.

Relative positioning of circuit elements in circuit design

Methods and apparatuses are disclosed for automatic orientation optimization in the course of generating a placed, routed, and optimized circuit design. Also disclosed are a circuit design and circuit created with the technology. Also disclosed are a circuit design and circuit created with the technology.

Method and apparatus for automatic orientation optimization

Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuits design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements.

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Sunnyvale, CA, United States of America

Anand Arunachalam