Imec Vzw

Imec

Taiwan Semiconductor Manufacturing Comp. Ltd.

Samsung Electronics Co., Ltd.

Texas Instruments Corporation

Koninklijke Philips Corporation N.v.

Vrije Universiteit Brussel

Interuniversitair Microelektronica Centrum (imec)

Imec Zvw

Nxp B.v.

Anabela Veloso

Shou-Zen Chang

Eric Beyne

Boon Teik Chan

Geert Eneman

Trong Huynh Bao

HongYu Yu

Julien Ryckaert

Jorge Adrian Kittl

Liesbeth Witters

Hag-Ju Cho

Stefan Kubicek

Raf Appeltans

Anne Lauwers

Nadine Collaert

Rita Rooyackers

Naoto Horiguchi

Vasile Paraschiv

Min-Soo Kim

Basoene Briggs

Marcus Johannes Henricus Van Dal

Anne Jourdain

An De Keersgieter

Guglielma Vecchio

Paola Favia

Anil Kottantharyil

Rongmei Chen

Philippe Matagne

Hong Yu Yu

Anil Kottantharayil

A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

Strained semiconductor monocrystalline nanostructure

A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

Method of producing an integrated circuit chip including a back-side power delivery network

The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having vertical channel field-effect transistor (FET) devices comprises forming on a substrate, a plurality of semiconductor structures protruding vertically from a lower source/drain semiconductor layer of the substrate. The semiconductor structures can be arranged in an array having a plurality of rows and columns. The method can include etching metal line trenches between at least a subset of the rows and forming metal lines in the metal line trenches to contact the lower source/drain layer. The method can also include forming gate structures at least partly enclosing semiconductor structure channel portions located above the lower source/drain layer and forming upper source/drain metal contacts on semiconductor structure upper source/drain portions located above the channel portions.

Method of forming a semiconductor device

A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET

The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion. The method additionally comprises forming on the channel portion an epitaxial semiconductor stressor layer enclosing the channel portion, wherein the stressor layer and the channel portion are lattice mismatched, forming an insulating layer and a sacrificial structure, wherein the sacrificial structure encloses the channel portion with the stressor layer formed thereon and wherein the insulating layer embeds the semiconductor structure and the sacrificial structure, forming in the insulating layer an opening exposing a surface portion of the sacrificial structure, and etching the sacrificial structure through the opening in the insulating layer, thereby forming a cavity exposing the stressor layer enclosing the channel portion. The method further comprises, subsequent to etching the sacrificial structure, etching the stressor layer in the cavity, and subsequent to etching the stressor layer, forming a gate stack in the cavity, wherein the gate stack encloses the channel portion of the vertical semiconductor structure.

Method of forming vertical field effect transistor device

The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

Vertically stacked semiconductor devices having vertical channel transistors

The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure. Thereafter, the exposed target layer is removed along the upper portion of the sidewall surface of the vertical nanostructure selective towards the protection layer. Thereafter, the remaining protection layer is removed.

Method of forming target layer surrounding vertical nanostructure

A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

Method for manufacturing a CMOS device and associated device

An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Method for forming a transistor structure comprising a fin-shaped channel structure

A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Semiconductor device and method for fabricating the same

A semiconductor device is disclosed that comprises a fully silicided electrode formed of an alloy of a semiconductor material and a metal, a workfunction modulating element for modulating a workfunction of the alloy, and a dielectric in contact with the fully silicided electrode. At least a part of the dielectric which is in direct contact with the fully silicided electrode comprises a stopping material for substantially preventing the workfunction modulating element from implantation into and/or diffusing towards the dielectric. A method for forming such a semiconductor device is also disclosed.

Semiconductor device with reduced diffusion of workfunction modulating element

One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed. The method further comprises removing the sacrificial cap layer from each of the at least one gate electrode, yielding each of the at least one gate electrode still having the given height.

Method for gate electrode height control

A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume above a gate dielectric. The volume is designed to substantially contain the fully silicided gate.

Method for forming a fully silicided gate and devices obtained thereof

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Leuven, Belgium

Anabela Veloso