Samsung Electronics Co., Ltd.

Konkuk University

An-Soo Park

Kang-yoon Lee

Jae-Sup Lee

Joon-Sung Park

Young-Gun Pu

Sung-Hoon Kim

Pan-Suk Kwak

Kang-Yoon Lee

A vertical memory device and a method of manufacturing the same, the device including a cell array including cell regions spaced apart from each other in a second direction, each cell region including a regularly arranged plurality of vertical channels; bit-lines extending in the second direction, the bit-lines being spaced apart from each other in a first direction crossing the second direction; and bit-line contacts respectively electrically connecting the vertical channels and the bit-lines, wherein each cell region includes a sub isolation region configured to electrically isolate the cell region in the second direction, the sub isolation region extending in the first direction, the vertical channels are classified into a plurality of types according to a distance from the sub isolation region in the second direction in each cell region, and the bit-line contacts are configured to electrically connect each bit-line to at least two vertical channels having different types.

Vertical memory devices and methods of manufacturing vertical memory devices

A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.

Digital phase locked loop device and method in wireless communication system

A Time-to-Digital Converter (TDC) is provided. The TDC includes a first TDC unit for receiving a first input signal and a second input signal, delaying the first input signal on a specific time basis using each of first delay blocks, generating first phase-divided signals by performing first phase division on signals of input/output nodes for each of the first delay blocks on a predefined Phase-Interpolation (PI) delay time basis, and outputting the second input signal and a phase-divided signal closest to the second input signal, among the first phase-divided signals, a time amplifier for independently time-amplifying the second input signal and the phase-divided signal closest to the second input signal, and a second TDC unit for delaying a phase-divided signal closest to the time-amplified second input signal on a specific time basis using each of second delay blocks, and generating second phase-divided signals by performing second phase division on signals of input/output nodes for each of the second delay blocks on a predefined PI delay time basis.

Time-to-digital converter and operation method thereof

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Seoul, South Korea

An-Soo Park