Faraday Technology Corporation

An-Ru Andrew Cheng

Huan-Yung Tseng

Tzu-Chun Liu

Chang-Song Lin

Chih-Hung Chen

Kwo-Jen Liu

Kai-Jen Ko

Jie-Hong Wang

An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.

Integrated circuit capable of locating failure process layers

A method for testing latch-up phenomenon of a chip is provided. The chip is tested on a test platform, the test platform storing a test program of the chip for testing the chip. The method includes (a) obtaining the test program of the chip tested on the test platform, (b) obtaining pin data of the chip by the test program of the chip, (c) setting up an input pin of the chip with an initial value, and (d) providing a test current to the pin of the chip, and then measuring the current between a power end and a ground end of the chip to see if it exceeds a first predetermined value.

Universal test platform and test method for latch-up

A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an &ldquo;ON&rdquo; state having a threshold voltage at a first value. At least one layer of metal interconnection is formed over the first dielectric layer within the ROM region and Is covered by a second dielectric layer. A coding photoresist layer is formed on the second dielectric layer and patterned to form a plurality of apertures defining exposure windows. Using the patterning coding photoresist layer as a dielectric etching and implantation hard mask, the underlying field-effect transistors to be coded permanently to a logic &ldquo;OFF&rdquo; state through the apertures, thereby raising the threshold voltage of the field-effect transistors to a second value.

Method for minimizing product turn-around time for making semiconductor permanent store ROM cell

Growing community of inventors

Hsin-Chu, Taiwan

An-Ru Andrew Cheng