Realtek Semiconductor Inc.

An-Ming Lee

Chao-Cheng Lee

Yu-Pin Chou

Tzu-Chien Tzeng

Tzuo-Bo Lin

Yueh-Hsing Huang

Wu-Chih Lin

Bo-kai Huang

Ying-Hui Zhu

Chia-Liang (Leon) Lin

Chien-Wen Chen

Cheng-Yu Chen

Yu-Hsiang Chen

Chih-Ching Chien

Leaf Chen

Yao-Chia Liu

Bo-Yu Chen

Ming-Hui Tung

Pei-Si Wu

Tsung-Yen Liu

Guan-Yu Chen

Chin-Wei Huang

Chun-Ting Liao

I-Hsun Huang

Yo-Hao Tu

Jun-Jie Xie

Chun-Wei Yang

Zhen-Guo Sun

Female connector

Male connector

An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.

Frequency doubling apparatus and method thereof

A timing control device and a timing control method for a high frequency signal system, the timing control method respectively control trigger points of reset signals, and process the controlled reset signals and clock signals to obtain a signal group with having an absolute timing relationship.

Timing control device and method for high frequency signal system

A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.

Integrated circuit device and system on a chip (SOC) for reducing boot time

A switch and a multiplexer including the same are provided, which are applicable to selectively transmit the high frequency signal from an input terminal to an output terminal therethrough. The switch includes a switch device and a variable resistor. The switch device is connected between the input terminal and the output terminal, and the switch device includes a control terminal and is configured to be switched between ON and OFF according to a switch controlling signal provided to the control terminal. The variable resistor is connected to the control terminal and configured to change to a first resistance while the switch device is ON, and to change to a second resistance while the switch device is OFF according to a resistor controlling signal. The first resistance is higher than the second resistance, and the resistor controlling signal is changed corresponding to the switch controlling signal.

Switch and multiplexer including the same

An equalizer includes a first sampler, a second sampler, and an equalization circuit. The first sampler is used for sampling an input data to generate an output data, and the second sampler is used for sampling the input data to generate an edge information. The equalization circuit is coupled to the first sampler and the second sampler, and includes an equalization unit and a control unit. The equalization unit performs an equalization operation on an original input data in order to generate the input data according to a plurality of tap coefficients. The control unit is coupled to the equalization unit, for adjusting the plurality of tap coefficients according to the output data and the edge information.

Equalizer and signal receiver thereof

The present invention disclosed a Universal Serial Bus (USB) apparatus. The apparatus includes: a signal detecting unit for detecting a packet signal transmitted from a USB host and generating an acknowledgment signal according to a detection result; an error detecting unit, coupled to the signal detecting unit, for generating a control signal according to the acknowledgment signal; and a frequency generating unit, coupled to the error detecting unit, for generating an output clock signal according to the control signal.

USB apparatus

The present invention discloses a signal receiving method for determining a transmission format of an input signal and a related signal receiving circuit. The signal receiving method includes: receiving the input signal; generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and determining the transmission format of the input signal according to the signal detecting result. The signal receiving circuit includes: an input interface, for receiving an input signal; a detecting module, for generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and a determining unit, for determining the transmission format of the input signal according to the signal detecting result.

Signal receiving method for determining transmission format of input signal and related signal receiving circuit

A communication system capable of adjusting power consumed thereby is adapted for receiving connection information. The communication system includes first and second transceiving devices. The first transceiving device includes a transmitting end and a service end for receiving the connection information. The second transceiving device includes a receiving end capable of forming a communications link with the transmitting end. A power state of each of the first and second transceiving devices is switchable between a power-supplied mode and a power-saving mode. The power state alters status of the communications link.

Communication system capable of adjusting power consumed thereby

A control apparatus for accessing a memory card includes a bus, a detecting circuit, and an adjusting circuit. The bus is regarded as a signal transmission line between the control apparatus and the memory card. The bus has a power signal transmission line for providing the memory card with a power signal. The detecting circuit detects an operating status of the control apparatus and generates an indication signal when the operating status exceeds a predetermined operating range. The adjusting circuit is coupled to the bus and detecting circuit, and is utilized for adjusting a current passing through the power signal transmission line according to the indication signal without closing the power signal transmission line thereby making the operating status operated within the predetermined operating range.

Memory card control apparatus and protection method thereof

The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

Signal receiving circuit adapted for multiple digital video/audio transmission interface standards

The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/discharging on another end to control the gate of the second field effect transistor; a second switch for controlling charging/discharging of the second capacitor device based on the first set of control signal; and a second current source providing charging current for the second capacitor device. The present invention adjusts output voltage slew rate of the output circuit by adjusting the time constant of the first and second capacitor devices.

Output circuit for adjusting output voltage slew rate

A multi-phase clock generator for generating a set of multi-phase clock signals is disclosed. The multi-phase clock generator includes a signal generator, a phase adjusting circuit, and a phase interpolator. The signal generator generates a plurality of first clock signals according to a reference clock signal. The phase adjusting circuit, which is a phase rotator or a phase selecting circuit and coupled to the signal generator receives the first clock signals and adjusts the phases of the first clock signals according to a control signal to generate a plurality of second clock signals. The phase interpolator, which is coupled to the phase adjusting circuit, interpolates the second clock signals to generate the set of multi-phase clock signals.

Multi-phase clock generator and method thereof

The present invention discloses an impedance matching circuit with automatic adjustment and a method thereof. The impedance matching circuit comprises: a resistor, for receiving a reference voltage and generating a reference current; a detection unit, for detecting resistance variation and generating a plurality of comparison voltages according to said reference current; a comparison unit, for comparing said reference voltage with said comparison voltages, and generating a control signal; and a composite resistor unit, for receiving said control signal and generating a matched impedance. Therefore, a matched impedance value can be obtained within a designed range in despite of the manufacturing process and the operation environment.

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Hsin-Chu Hsien, Taiwan

An-Ming Lee