Taiwan Semiconductor Manufacturing Comp. Ltd.

An-Ming Chiang

Kuei-Wu Huang

Fu-Hsin Chen

You-Kuo Wu

Wei-Kun Yeh

Hua-Yu Yang

Chi-Hsiang Lee

Kuo-Ting Lee

The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second polarity type is formed on the buried layer. An isolation structure of the first polarity type is formed between the first and second epitaxial layers on the buried layer. A first well of the second polarity type is formed on the first epitaxial layer. A second well of the second polarity type is formed on the second epitaxial layer. A third well of the first polarity type is formed between the first and second wells, on the isolation structure. The isolation structure interfaces with the buried layer and the third well, thereby substantially blocking a leakage current path between the first and the second wells.

MOS device with a high voltage isolation structure

A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Tapered floating gate with nitride spacers to prevent reverse tunneling during programming in a split gate flash

An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N&plus; readout region, performed simultaneously with the formation of the N&plus; source/drain region of the reset transistor, however with the N&plus; readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P&plus; region, used as the top segment of the pinned photodiode structure, with the N&plus; readout region, surrounded by the P&plus; region. The placement of the N&plus; readout region, in a region of the pinned photodiode structure, eliminates the need for a transfer transistor, for the active pixel sensor cell, and results in a higher signal to noise ratio, as well as lower dark current generation, than counterparts fabricated without the use of the process, and structure, of this invention.

Pinned photodiode structure in a 3T active pixel sensor

Process for preventing the reverse tunneling during programming in split gate flash

Growing community of inventors

Hsin-Chu, Taiwan

An-Ming Chiang