Taiwan Semiconductor Manufacturing Comp. Ltd.

An-Min Chiang

Pei-Hung Chen

Yeh-Jye Wann

Wei-Kun Yeh

Chi-Hsiang Lee

You-Kuo Wu

Hua-Yu Yang

Shau-Tsung Yu

Shun-Liang Hsu

Fu-Hsin Chen

Jyh-Feng Lin

Hsin-Pai Chen

Kuo-Chin Hsu

Wei-kun Yeh

John C-s Wei

Kuo-Ting Lee

Shaun-Tsung Yu

Long-Shang Juang

Chi-Shiang Lee

Wen-Hua Huang

A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

Isolation structure in field device

A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.

Method for forming an integrated circuit with high voltage and low voltage devices

A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

CMOS image sensor n-type pin-diode structure

A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures, with an extended region for source drains bordering photodiode regions. Ions are implanted to form photodiodes, overlapping the extended bordering source drain regions. A blanket transparent insulating layer is deposited.

Method of manufacturing for CMOS image sensor

A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.

Process for fabricating a high quality CMOS image sensor

A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

Opposite focus control to avoid keyholes inside a passivation layer

A process for fabricating a flash EEPROM device, incorporating a shallow, heavily doped, source side region, used to improve the endurance of the flash EEPROM device, has been developed. The process features placing a shallow, ion implanted arsenic region, in the semiconductor substrate, adjacent to one side of a floating gate structure, prior to creation of the control gate structure. The addition of the shallow, ion implanted arsenic region, improves the coupling ratio at the source, which in turn results in the ability of the flash EEPROM device to sustain about 1,000,000 program/erase cycles, compared to counterparts, fabricated without the shallow, source side region, only able to sustain about 400,000 program/erase cycles.

Method for improving the endurance of split gate flash EEPROM devices

A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

Oxidation method for removing fluorine gas inside polysilicon during

A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions. This prevents voids from forming at the gate electrode/ILD interface after the ILD layer is deposited and subsequent high-temperature processing steps are performed. The invention also reduces the enhanced boron diffusion in the P-FET gate oxide that can degrade the threshold voltage.

Method for preventing fluorine outgassing-induced interlevel dielectric

A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs on the same substrate by alternate photoresist masking and ion implantation. The self-aligned source/drain areas for the P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions that are implanted in the P-channel FET gate electrodes during the source/drain implant results in out-gassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which out-diffuses the fluorine atoms prior to depositing the ILD, and thereby prevents the formation of voids after the ILD is deposited and subsequent high-temperature process steps are performed.

Method for preventing delamination of interlevel dielectric layer over

A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer. The patterned second masking layer is then removed. The remaining lower lying metallization layer is then patterned through a Reactive Ion Etch (RIE) process using a patterned first masking layer and the patterned upper metallization layer as the etch mask.

Method of multi-step reactive ion etch for patterning adjoining

A new method of metal etching using a disposable metal antireflective coating process along with metal dry/wet etching is described. An insulating layer is provided over semiconductor device structures in and on a semiconductor substrate. Openings are made through the insulating layer to the semiconductor substrate and to the semiconductor device structures to be contacted. A barrier metal layer is deposited conformally over the insulating layer and within the openings. A metal layer is deposited over the barrier metal layer. The metal layer is covered with an antireflective coating. A layer of photoresist is coated onto the substrate and patterned to provide a photoresist mask. The antireflective coating, the metal layer and a portion of the barrier metal layer are etched away where the layers are not covered by the photoresist mask. The photoresist mask is removed. The remaining barrier metal layer not covered by the patterned metal layer is etched away whereby all the remaining antireflective coating is also removed completing the metal patterning in the fabrication of the integrated circuit.

Growing community of inventors

Hsinchu, Taiwan

An-Min Chiang