Taiwan Semiconductor Manufacturing Comp. Ltd.

An-Jhih Su

Hsien-Wei Chen

Der-Chyang Yeh

Chen-Hua Douglas Yu

Li-Hsien Huang

Chi-Hsi Wu

Wei-Yu Chen

Ming Shih Yeh

Ming-Shih Yeh

Ying-Ju Chen

Tien-Chung Yang

Wei-Cheng Wu

Shin-Puu Jeng

Hua-Wei Tseng

Tsung-Shu Lin

Po-Hao Tsai

Jing-Cheng Lin

Wen-Chih Chiou

Wei-yu Chen

Yu-Hung Lin

Yueh-Ting Lin

Chia-Nan Yuan

Tsang-Jiuh Wu

Shih-Peng Tai

Chin-Chuan Chang

Shih-Guo Shen

Jo-Mei Wang

Szu-Wei Lu

Jie Chen

Ta-Wei Liu

Tzu-Shiun Sheu

Chung-Shi Liu

Ming-Da Cheng

Hung-Jui Kuo

Li-Hui Cheng

Cheng-Hsien Hsieh

Tzu-Yu Wang

Lin-Chih Huang

Chi-Chun Hsieh

Shao-Yun Chen

Shang-Yun Hou

Hsiu-Jen Lin

Ying-Ching Shih

Chien Ling Hwang

Tsung-Ding Wang

Chih-Wei Wu

Hsien-Pin Hu

Hsin-Yu Pan

Jung Wei Cheng

Pu Wang

Guan-Yu Chen

Chia-Shen Cheng

Chih-Chien Pan

Chiang Lin

Kuan-Chung Lu

Chi-Jung Lee

Ching-Hua Hsieh

Wensen Hung

Kim Hong Chen

Hung-Pin Chang

Hsiang-Fan Lee

Szu-Po Huang

Shing-Chao Chen

Liwei Lin

Yan-Fu Lin

Chin-Hsien Chen

Hung-Jui Kou

Yung-Shou Cheng

In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

Semiconductor device and method

In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Semiconductor packages

A method of manufacturing a semiconductor device includes the following steps. A semiconductor substrate is provided. A plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. At least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. A plurality of conductive connectors are formed to electrically connect to the second conductive features. The semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.

Methods of manufacturing semiconductor devices

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

Devices employing thermal and mechanical enhanced layers and methods of forming same

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

Photonic integrated package and method forming same

A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Semiconductor structure and method of forming the same

A method for forming a chip package structure is provided. The method includes forming a first molding layer surrounding a first chip structure. The method includes disposing a second chip structure over the first chip structure and the first molding layer. The method includes forming a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The method includes forming a third molding layer surrounding the first molding layer and the second molding layer. The method includes disposing a third chip structure over the second chip structure, the second molding layer and the third molding layer. The method includes forming a fourth molding layer surrounding the third chip structure and over the second chip structure, the second molding layer, and the third molding layer.

Method for forming chip package structure with molding layer

A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Package structure including IPD and method of forming the same

Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Via for component electrode connection

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

Chip package structure with bump

A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Package structure and manufacturing method thereof

A method of manufacturing a semiconductor package includes forming an encapsulated semiconductor device and forming a redistribution structure over the encapsulated semiconductor device, where the encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. Forming the redistribution structure includes forming a first dielectric layer on the encapsulated semiconductor device, and forming a first redistribution circuit layer on the first dielectric layer by a plating process carried out at a current density of substantially 4˜6 amperes per square decimeter, where the first dielectric layer comprises a first via opening. An upper surface of the first redistribution circuit layer filling the first via opening is substantially coplanar with an upper surface of the rest of the first redistribution circuit layer.

Semiconductor package and method of manufacturing the same

A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

Package structure with bridge die laterally wrapped by insulating encapsulant and surrounded by through vias and method of forming the package structure

A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Fan-out structure and method of fabricating the same

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Structure and method of forming a joint assembly

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Taoyuan, Taiwan

An-Jhih Su