United Microelectronics Corp.

An-Hsiu Cheng

Ping-Chia Shih

Chi-Cheng Huang

Kuo-Lung Li

Chih-Hao Pan

Zi-Jun Liu

Hung-Wei Lin

Chuan-Fu Wang

Chun-Hung Cheng

Yu-Chun Chen

Ya-Sheng Feng

Chih-Hung Wang

Shu-Hung Yu

Chih-Yao Wang

Ling-Hsiu Chou

Chia-Hui Huang

Cheng-Hua Chou

Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

Semiconductor structure and method of forming the same

A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

Semiconductor memory device and fabrication method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

Semiconductor device and manufacturing method thereof

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Pingtung County, Taiwan

An-Hsiu Cheng