Hewlett-packard Development Company, L.P.

An Hien Lam

Sompong Paul Olarig

Ryan J Hensley

Jaideep Dastidar

Michael Ruhovets

Wiley R Flanakin

A system comprises a processor adapted to read BIOS code from a system ROM, a management controller coupled to the processor, and a network interface controller coupled to the management controller. The management controller selectively traps read accesses from the processor that target the system ROM and, in response, causes the network interface controller to load network BIOS code from storage external to the system during system initialization.

Networked basic input output system read only memory

A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

Inter-queue ordering mechanism

Back plane and mid-plane assemblies and related systems and methods are described. In one embodiment, a system comprises an enclosure and a plane assembly mounted within the enclosure and configured to connect with multiple pluggable devices. The plane assembly comprises a first plane portion having multiple connectors; and at least a second plane portion having multiple connectors, with the second plane portion being offset from the first plane portion.

Back plane and mid-plane assemblies and related systems and methods

A computer network employs a fault-tolerant or redundant switch architecture. The network includes redundant data paths coupling end nodes and switches. Fault-tolerant repeaters (FTRs) can be stand-alone devices or can be incorporated into the switches. Using error detection, the FTR checks to see if the data is good on all paths. If the data received on one path is 'bad' and the data is 'good' on another path, the FTR transmits the &#x201c;good&#x201d; data in place of the &#x201c;bad&#x201d; data. For any switch, a pair of incoming ports may be configured as redundant incoming ports and a pair of outgoing ports may be configured as redundant outgoing ports.

Fault-tolerant switch architecture

A digital isolation circuit comprises a plurality of CMOS transistors. The transistors may be connected together to form either a logic NAND gate or a logic NOR gate, but the isolation circuits preferably are not used to provide the NAND or NOR logic functions. The isolation circuit isolates one input data signal from an output signal in response to a control input signal. If the control signal is driven to one state (e.g., logic ), the isolation circuit can be made to function as an inverter when no isolation is needed. In the opposite logic state, the control signal causes the isolation circuit to isolate the input data signal from the output signal.

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Houston, TX, United States of America

An Hien Lam