Phison Electronics Corporation

Nvidia Corporation

An-Chung Chen

Chih-Ming Chen

Wen-Lung Cheng

Hung-Cheng Huang

Ming-Tse Lin

Wei-Yung Chen

Jen-Chu Wu

Kuen-Chih Lin

An exemplary embodiment of the present disclosure provides a reference clock signal generation method for a memory storage device. The method includes: receiving a first type signal from a host system; generating a first control parameter according to a frequency of the first type signal; receiving a second type signal from the host system after the first type signal is received; generating a second control parameter according to a frequency of the second type signal; and generating a reference clock signal meeting a first condition according to the second control parameter. Therefore, an efficiency of generating the reference clock signal can be improved.

Reference clock signal generation method, memory storage device and connection interface unit

A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.

Sampling circuit module, memory control circuit unit, and method for sampling data

A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Clock data recovery circuit module and method for generating data recovery clock

A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether the data having a specific frequency is inputted is detected. If not, the setting code stored in the register circuit is read, such that an oscillator circuit module of the memory storage apparatus generates a first reference frequency based on the first setting information. If yes, the setting code stored in the register circuit is updated by a second signal transmission path, and the updated setting code is read, such that the oscillator circuit module generates a second reference frequency based on a second setting information. The updated setting code includes the second setting information.

Reference frequency setting method, memory controller and memory storage apparatus

A signal processing method, a connector and a memory storage device are provided. The signal processing method is for the connector which does not include a crystal oscillator. The signal processing method includes: receiving a first signal stream from a host system; tracking a transmission frequency of the first signal stream, and obtaining a frequency shift quantity of the first signal stream relative to the transmission frequency; determining if a spread spectrum operation is performed on the first signal stream according to the frequency shift quantity to generate a determination result; generating a second signal stream according to the determination result and the transmission frequency. Accordingly, the spread spectrum operation is handled under the situation without a crystal oscillator.

Signal processing method, connector, and memory storage device

A reference frequency setting method of a flash memory storage apparatus is provided. The flash memory storage apparatus includes a flash memory module, a storage unit, and an oscillator circuit without a crystal. The reference frequency setting method includes following steps. Whether a setting code is stored in the flash memory module or the storage unit is determined, wherein the setting code includes information of a reference frequency. If the setting code is stored in the flash memory module, the setting code is read to allow the oscillator circuit to generate the reference frequency according to the setting code. A memory controller and a flash memory storage apparatus using the reference frequency setting method are also provided.

Reference frequency setting method, memory controller, and flash memory storage apparatus

A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.

Clock data recovery circuit

A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate a reference clock signal. The PLL unit is used to increase a clock frequency of the reference clock signal to generate a PLL clock signal. The data receiver is used to compare the PLL clock signal with a clock signal of an input data stream, so as to output a voltage adjusting signal to the voltage controlled oscillator. The voltage controlled oscillator adjusts the clock frequency of the reference clock signal to be generated according to the reference clock signal, so as to lock the clock frequency of the PLL clock signal to a base frequency of the clock signal of the input data stream.

Method and data transceiving system for generating reference clock signal

A bandgap reference circuit having a low sensitivity to temperature and supplied voltage installs a compensation circuit on a bandgap reference circuit to substitute a prior art that uses a resistor to match the circuit startup purpose and solve the problem of startup error caused by the manufacturing error. The bandgap reference circuit includes a first amplifier, a second amplifier, and a reference circuit having a plurality of transistors and a plurality of bipolar junction transistors, and the bandgap reference circuit is electrically connected to a same supplied power of which the reference circuit is electrically connected and also includes a plurality of transistors and a compensation circuit of the second amplifier, so as to output a stable startup voltage which has a low sensitivity to the change of temperature and the change of supplied voltage.

Growing community of inventors

Hsinchu, Taiwan

An-Chung Chen