United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

An-Chi Liu

Chun-Hsien Lin

Yu-Cheng Tung

Cheng-Pu Chiu

Yi-Wang Jhan

Tien-Cheng Lan

Ssu-I Fu

Fu-Che Lee

Shih-Hung Tsai

Gang-Yi Lin

Te-Chang Hsu

Nan-Yuan Huang

Yu-Chih Su

Chih-Yi Wang

Tien-Shan Hsu

Chi-Hsuan Cheng

Chien-Ting Lin

Chih-Wei Chen

Wen-Tai Chiang

Ying-Tsung Chen

Kuan-Lin Chen

Tsung-Chieh Yang

Yi-Wei Chen

En-Chiuan Liou

Li-Wei Feng

Chih-Kai Hsu

Yu-Hsiang Hung

Jyh-Shyang Jenq

Kuo-Chih Lai

Kun-Yuan Liao

Chao-Hung Lin

Nien-Ting Ho

Chin-Yang Hsieh

Shih-Fang Hong

Chao-Ching Hsieh

Shin-Chi Chen

Hsiao-Pang Chou

Yao-Jhan Wang

Chih-Yueh Li

Chien-Cheng Tsai

Yifei Yan

Ming-Feng Kuo

Hon-Huei Liu

Chia-Hsun Tseng

Chih-Chung Chen

Huixian Lai

Kuei-Hsuan Yu

Chih-Wei Wu

Chih-Chun Wang

Mei-Chen Chen

Hsin-Hsing Chen

Chun-Min Wang

Pei-Ching Yeh

Chi-Heng Lin

Bao-Tzeng Huang

Chih-Wen Teng

Tzu-Yu Tseng

Chih-Chien Huang

Junyi Zheng

A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Magnetoresistive random access memory with metal oxide layer on top surface and sidewall of MTJ

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

High electron mobility transistor

The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Semiconductor device and method of forming the same

A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Semiconductor structure and method for forming the same

Magnetoresistive random access memory with protrusions on sides of metal interconnection

A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Memory device and fabrication method thereof

The invention provides a contact plug structure. The contact plug structure comprises a substrate and a dielectric layer, and a first contact hole located in the dielectric layer and penetrating into the substrate, the first contact hole has a first through hole portion located in the dielectric layer and a first groove located in the substrate, and the first through hole portion is communicated with the first groove, the maximum width of the first groove is larger than that of the first through hole portion in the direction parallel to the substrate surface. A barrier layer at least partially covering the sidewall of the first groove. A conductive pad layer is located on the bottom surface of the first groove. The conductive core layer is arranged on the conductive pad layer, and the barrier layer wraps the conductive pad layer and the conductive core layer.

Contact plug structure and manufacturing method thereof

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a first passivation layer adjacent to two sides of the gate electrode, and a p-type semiconductor layer between the gate electrode and the barrier layer. Preferably, a corner of the p-type semiconductor layer contacting a sidewall of the first passivation layer includes a first curve, and a bottom surface of the p-type semiconductor layer directly on the first passivation layer includes a second curve.

A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.

Magnetoresistive random access memory

A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

Method for fabricating tunneling field effect transistor having interfacial layer containing nitrogen

A method for forming a tunneling field effect transistor is disclosed, which includes the following steps. First, a semiconductor substrate is provided. A source region is formed on the semiconductor substrate. A tunneling region having a sidewall and a top surface is formed on the source region. A drain region is formed on the tunneling region. A gate dielectric layer is then formed, covering the sidewall and the top surface of the tunneling region. A first metal layer is formed, covering the gate dielectric layer. Subsequently, an anisotropic etching process is performed to remove a portion of the first metal layer. After the anisotropic etching process, a second metal layer is fabricated to cover the remaining first metal layer and the gate dielectric layer.

Tunneling field effect transistor and method of fabricating the same

Tunneling field effect transistor having interfacial layer containing nitrogen

A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

Semiconductor structure with a bump having a width larger than a width of fin shaped structures and manufacturing method thereof

A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

Insulating layer next to fin structure and method of removing fin structure

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Tainan, Taiwan

An-Chi Liu